いた。鎖の両端をそれぞれ A と B ，また A から x 離れた点を P とする。 B を力 F で水平に引っ張ると全体が加速度 a で動いた。
19-1. 運動の様子を図示せよ。点 P における鎖の張力を S とする。 【解答】右図の通り。図の S は， A ∼ P 部分を右に引く張力である。もちろ ん実際には P で鎖はくっついているが， S が A ∼ P 部分に働くことを明らか にするため少し離して書いた。図の左向きの力は， S の反作用であり， P ∼ B 部分を左に引いている。
a core are propagated to all input ports of the core from TPS, and the test responses appeared at an out- put port of the core are propagated to TRS consecu- tively at the speed of system clock. The propagation of test patterns and responses is achieved by using interconnects and consecutively transparent paths of surrounding cores. All interconnects can be tested in a similar fashion. Therefore, it is possible to apply any test sequence and observe any response sequence consecutively at the speed of system clock. We also proposed a design-for-testability method for making a given SoC consecutively testable based on integer linear programming problem. Our future work is to propose a DFT method for making cores consecutively transparent with minimum hardware overhead.
To increase the testability of the complete design and to ease RT-level test generation, various DFT methods at RT-level have also been proposed. The most com- mon methods are based on full-scan or partial scan. However, a scan-based DFT technique leads to long test application time and it is less useful for at-speed testing. On the other hand, non-scan DFT technique [ 6 , 9 , 13 , 14 , 30 , 37 ] offer low test application time and they facilitate at-speed testing. In [ 6 ], non-scan DFT techniques are proposed to increase the testability of RT-level designs. In [ 30 ], the authors presented a method called orthogonal scan. It uses functional data- path flow for test data, instead of traditional scan-path flow; therefore, it reduces test application time. In [ 13 ], a technique was proposed to improve the hierarchical testability of the data path, which can aid hierarchi- cal test generation. In [ 14 ], the authors presented a DFT technique for extracting functional control- and data-flow information from RT-level description and illustrated its use in design for hierarchical testability. This method has low overhead and it leads to shorter test generation time, up to 2–4 orders of magnitude less than traditional sequential test generation due to the use of symbolic test generation. In [ 37 ], the au- thors presented a method based on strong testability, which exploits the inherent characteristic of datapaths to guarantee the existence of test plans (sequences of control signals) for each hardware element in the datapath. Compared to the full-scan technique, this method can facilitate at-speed testing and reduce test application time. However, it introduces hardware and delay overhead. To reduce overhead, the authors pro- posed a linear-depth time-bounded testability-based DFT method in [ 9 ]. It ensures the existence of a linear- depth time expansion for any testable fault and exper- iments showed that it offers lower hardware overhead than the method in [ 37 ].
Received: 14 November 2011 / Accepted: 26 June 2012 / Published online: 13 July 2012 # Springer Science+Business Media, LLC 2012
Abstract The paper proposes a hierarchical untestable stuck-at fault identification method for non-scan synchro- nous sequential circuits. The method is based on deriving, minimizing and solving test path constraints for modules embedded into Register-Transfer Level (RTL) designs. First, an RTL test pattern generator is applied in order to extract the set of all possible test path constraints for a module under test. Then, the constraints are minimized using an SMT solver Z3 and a logic minimization tool ESPRESSO. Finally, a constraint-driven deterministic test pattern gener- ator is run providing hierarchical test generation and untest- ability proof in sequential circuits. We show by experiments that the method is capable of quickly proving a large num- ber of untestable faults obtaining higher fault efficiency than achievable by a state-of-the-art commercial ATPG. As a side effect, our study shows that traditional bottom-up test
8 Aqua Restoration Research Center Kawashima Kasada-machi Kakamigahara-City Gifu Prefecture, 501-6021,
9 Water Resources Environment Technology Center, Tokyo, Japan.
We conducted complimentary analysis for fish fauna covering the entire Japanese archipelago as well as the specific regions such as Hokkaido and Kyushu. The results were compared with the protected areas (national parks and other reserves) to see the gaps between them. Although important areas found by the complimentary analysis in Hokkaido were relatively covered by the current reserves, those in Kyushu were not protected. There is a bias of data availability in Kyushu, and therefore we should fill the gaps of database using niche models for various species before complimentary analysis. Sediment control dams and water reservoir constructions and gravel mining are causing progressive sediment starvation in Japanese rivers, which results in rapid degradation of the riverbeds followed by forest expansion. Benthic invertebrates and fish cannot survive there, and migrating fish lose their spawning habitat. Bar-braided channels are changed to single-thread channels, and thereby habitats for overwintering juvenile fish will disappear. The bars and floodplains are covered by trees, because flood disturbances are greatly reduced by dams. The forest expansion has indirect impacts on material flows and organisms in the rivers and floodplains. It may reduce primary production and water temperature, and increase allochthonous input, which affect invertebrates and fish. Not only aquatic organisms, terrestrial animals, such as birds and mammals, also suffer from various impacts of forest expansion. The maximum stream temperature in summer may rise associated with dam construction and global warming. We focused on whitespotted char and Dolly varden as an indicator species, and build a niche model to predict shrinkage of their distribution by those impacts.
9 = 16). Therefore,
we can relax the constraints by considering the test require- ments for each core separately using different variables. (Cost for Transparency) During the optimization of transparency-based TAM design, we have to consider two types of cost. One is the area overhead for making cores transparent and the other is the routing overhead for ad- ditional interconnect. The former cost can be determined within each core while the latter cost depends on the global layout information, and therefore it is difficult to compare these costs. The method in  considers that the area over- head for making cores transparent is negligible and tries to minimize only the number of additional interconnects. However, we can get better solution if we know the relative costs between the above two types of cost and both costs can be taken into account simultaneously during the opti- mization.