[PDF] Top 20 C216 2010 4 DDECS 最近の更新履歴 Hideo Fujiwara

... E-mail: {ohtake, hiroshi-i, fujiwara}@is.naist.jp Abstract—This paper proposes a new synthesis method for propagating information of paths from register transfer level (RTL) to gate level. The method enables false ... 完全なドキュメントを参照

... Science City, 630-0192 Japan. *{norlina,ooichiayee,zuri}@fke.utm.my, +fujiwara@is.naist.jp ABSTRACT This paper introduces a new class of assignment decision diagrams (ADD) called thru-testable ADDs based on a ... 完全なドキュメントを参照

... modes applied (TM) by the proposed method in Columns 2, 3, and 4, respectively. The column heading Original indicates the case when the original functional test sequence is applied on a given design, whereas the ... 完全なドキュメントを参照

... Keywords - scan design; shift register equivalents; security; testability; cardinality; enumeration. I. I NTRODUCTION Both testability and security of a chip have become primordial to ensure its reliability and ... 完全なドキュメントを参照

... MU X 1 in Figure 4. E. Algorithm for identification For an RTL circuit, the proposed method traverses RTL paths from each primary input or register until reaching a primary output or a register with depth-first ... 完全なドキュメントを参照

... January 2010 © Springer Science+Business Media, LLC 2009 Abstract Functional test sequences are often used in manufacturing testing to target defects that are not de- tected by structural ... 完全なドキュメントを参照

... Fig. 6 (a) Single-core bypass path by IEEE 1500 wrapper. (b) Multi-core bypass path by IEEE 1500 wrapper. of making cores transparent as well as the cost of additional interconnect area simultaneously during ... 完全なドキュメントを参照

... Abstract—Today’s digital circuits demand both high speed performance and miniaturization of chip size. As a result, delay fault testing has become very important to verify the quality requirements of VLSI chips. Full ... 完全なドキュメントを参照

... Several false path identification methods at gate level for combinational circuits[1], [2], [3] and for sequential circuits[4], [5] have been proposed. However, since it is dif- ficult to apply false path ... 完全なドキュメントを参照

... 2.1 Related Works Several DFT techniques at RTL have been proposed, most are scan-based. Gupta et al. [3] introduced a structured partial scan design that converts only the selected flip-flops into scan flip-flops. ... 完全なドキュメントを参照

... 1. Introduction In recent years, very large scale integrated circuit (VLSI) testing has become increasingly important because of the rapidly increasing number of gates on VLSIs and the grow- ing complexity of VLSIs due ... 完全なドキュメントを参照

... Keywords—design-for-testability; scan design; shift register equivalents; security; scan-based side-channel attack. I. I NTRODUCTION The design of secure chips demands protection of secret information, which may cause ... 完全なドキュメントを参照

... Table 4 shows the result of false path mapping and the time required for this mapping. Rows “#Ptotal”, “#Pfalse”, “Ratio”, “Total”, “Unique”, “Ravi”, “FEchk”, “Pwhole” and “Pfalse” show the total number of paths, ... 完全なドキュメントを参照

... Table 1 describes the test application time and test power reductions for the test set using MT-filling. Since TetraMAX cannot realize MT-filling to the test vectors for PIs, we apply MT-filling after test generation. ... 完全なドキュメントを参照

... number of LSSD scan elements, it involves high area and performance overhead. To resolve these problems, several scan-based approaches have been proposed. These can be classified into two categories: partial scan and full ... 完全なドキュメントを参照

... Hence the proposed heuristic does not suffer from any strain related to time and space. 7. EXPERIMENTAL RESULTS The experiments are carried out on ITC99 and ISCAS89 circuits. The algorithm is implemented in C++. Scan in- ... 完全なドキュメントを参照

... Several works have been proposed to solve this challenging problem. A scan-chain design based on scrambling was proposed in [4], [5]. In this method, flip-flops are dynamically reordered in a scan chain. An ... 完全なドキュメントを参照

... Some examples of the TPS movements are also shown in Fig. 7. According to the result of an aging analysis, a TPS can move from the scheduling table to the first level danger table like the TPS 9, but can jump to a two or ... 完全なドキュメントを参照

... For example, property p1 can be beneficial in activating the test sequence for value justification (step A of the FSM test generation, mentioned above). Assume that we need to justify state E, which is the only state ... 完全なドキュメントを参照

... To evaluate the correlation between the proposed extended fault model and the stuck-at fault model, an experiment as shown in Figure 4 is set up. Besides showing that the new functional fault model contributes to ... 完全なドキュメントを参照