[PDF] Top 20 J125 e IEICE 2006 3 最近の更新履歴 Hideo Fujiwara J125 e IEICE 2006 3

... Fig. 2 CUT and observe intervals. Fig. 3 Scan out and observed results. Fig. 4 Successful observation. The PG, e.g. an LFSR, returns to initial state after gen- erating the last pattern. The initialization ... 完全なドキュメントを参照

... 3.1 Benchmark circuit We used a ME circuit of an MPEG-2 system implementing heuristic 2-stage motion estimation with half-pixel accuracy. The circuit consists of a first-stage processing element (PE) array, which ... 完全なドキュメントを参照

... 4.2 Overview The aim of this algorithm is to find the minimum number of levels of cliques. Since the problem is NP- hard, we use a heuristic algorithm shown in Fig. 7. We first construct the compatibility graph G with ... 完全なドキュメントを参照

... t or the test pattern for f reaches the inputs of M. If the test pattern of f reaches inputs of M at time t , then f is activated and an error appears an output of M. The output of M at time t can be observed at a ... 完全なドキュメントを参照

... All pseudo-primary inputs (PPIs) corresponding t o the same scan flip-flop group are merged into a single PPI. As shown in Figure 1, each of the primary inputs shares the s[r] ... 完全なドキュメントを参照

... Delete po from PO if the path list P(po) has been empty.[r] ... 完全なドキュメントを参照

... Definition 6: A test group consists of a subset of modules in an SOC that are tested simultaneously. B. Effect of Test Frequency Reductions In typical SOC testing, due to the design characteristics such as heat ... 完全なドキュメントを参照

... Section 3, the optimization problems for both fault- independent two-pattern test and fault-dependent two-pattern test are formulated for state-observable FSMs, and their test generation methods are ... 完全なドキュメントを参照

... In order to reduce the hardware area overhead, the number of flip-flops to be converted into scan flip-flops should be reduced. To achieve the objective, several partial scan techniques have been introduced. Among all, ... 完全なドキュメントを参照

... An example of the method proposed in [10] and an ex- ample of the proposed DFT method are shown in Figure 2 and 3, respectively. Suppose that MUX m1 exists on a control path (dotted line) for ADD1. In order to ... 完全なドキュメントを参照

... 2. Observing Responses by a Slow Speed Tester Before providing a formulation of the problem we de- scribe the method given in [19] that can identify all failing responses by observing scan outputs even if the CUT test ... 完全なドキュメントを参照

... Index Terms—Acyclic test generation, design-for-test, sequential circuits, test generation complexity. I. INTRODUCTION est generation even for combinational circuits, was shown to be NP-complete almost three decades ago ... 完全なドキュメントを参照

... ログラムテンプレートとは，オペランドの値が未決定 のテストプログラムであり，テスト対象モジュールに 対し，テストパターンの正当化及びテスト応答の観測 を行う命令列からなる．この手法では，テンプレート に 対 し ，い く つ か の ラ ン ダ ム パ タ ー ン を オ ペ ラ ン ド に与えたシミュレーション結果から回帰解析により制 ... 完全なドキュメントを参照

... Fig.2 Parallel connection of memories Serial connection allows memories with the same bit width to be connected. Figure 3 shows an example of four serially connected 8x32 word memories. In this example, the four ... 完全なドキュメントを参照

... Kouhei OHTANI † , Satoshi OHTAKE †† , and Hideo FUJIWARA †† あらまし 本論文では，組合せ回路のノンロバストテスト可能なパス遅延故障に対するテスト生成を，縮退故 障用のテスト生成アルゴリズムを用いて行う方法を提案する．具体的には与えられた組合せ回路をパスリーフ化 ... 完全なドキュメントを参照

... 4. GOS in the PMOS of the static inverter To activate the GOS when the defect affects the PMOS of the central static inverter Pi, the voltage level at the gate of the transistor should be at the low level. In other ... 完全なドキュメントを参照

... Chikateru JINNO †∗ , Michiko INOUE † , and Hideo FUJIWARA † あら まし 本論文では ，ホールド と スイッチの機能を考慮し て ，内部平衡構造を拡張し た順序回路のクラスで ある内部切換平衡構造を提案する．提案するクラスは ，組合せテ スト 生成複雑度でテ スト 生成可能であり，平衡 ... 完全なドキュメントを参照

... Email:{yuuki-y, ohtake, fujiwara}@is.naist.jp Abstract In this paper, we present an approach to reduce over- testing of path delay faults (PDFs). To reduce test gen- eration complexity, design-for-testability ... 完全なドキュメントを参照

... There huge number techniques have investigated low cost test. Some methodologies [1-4] explore new scan architectures. The method in [1] effectively reduces test data volume and test application time for designs with ... 完全なドキュメントを参照

... parture from those in [2]. In this paper we assume that a BIST pretest is first con- ducted in order to rid of all chips that fail it. Only chips whose BIST circuitry has passed the pretest are kept, while the rest are ... 完全なドキュメントを参照