1-4244-9707-X/06/$20.00 ©2006 IEEE
24th IEEE International Conference on Computer Design (ICCD'06), pp. 446-451, October 2006.
c
b
the target path
a
d
additional path the original circuit
e e’
d’
c’
b’
a’
U0
X0 X1
XX
S0 (1,0) (0,1) S1
U1
U
j
j i
O
O O
2
1 2
(b) i
O1
(a)
remaining faults, delete all covered paths from the lists based on separate (4) generate a new test t’ for p under the constraints given in the test t;
1 1 1
t = t’; delete p from P(po ). If P(po ) has been empty, delete po from PO .r
output cones. Delete po from PO if the path list P(po) has been empty.r 1. While the fault list is not empty, do 2, 3, 4
2. Set PI as the empty set; select a path p whose sink node is po; generate a test t for the path delay fault; add all primary inputs that have been
(3) dtc =0, select a path from P(po );1
test−compaction−with−output−cone( )
3. while (dtc=0), do /* further compaction is possible. */
4. fault simulation with the test t on the selected testable path circuit for the f(po)=1
assigned specified values to PI; dtc=0, ;
(1) dtc =1; for each primary output po in PO , if , (2)(3)(4);1 f(po1)=1 reach(po1)
(2) for each pi in PI, if pi is not in , ;f(po1)=1 r
10 D
0x C
11 B
10 A
10 10 F
E
G 10 11
11 I
H
(a)
01
B x1
D x1
01 F E
01 x1
(b) G
H
I C
A
x1 01
1
2 A
A B
C1
C2 E
F1
F2
conflict (a)
conflict S1
A
P 1
S0
P 3 B
P 2
S1
C B
S0 S1 D
S1 P 1
P 2
(b) conflict
f
A
circuits
static fsim paths
static comp
paths detected
s13207 s9234 s5378 s1423
paths
robust
atpg
7.0 paths
detected
1107 54.07 467 46.96
2215 20.41 4.72 487 108 108
1.12 209 8.53 5.85
7.42 1044 91 68
non−robust
8.28 1.53 6.67 fsim
5525 atpg 2.3
2.1 42
2439 195.2 162 54 4009 1238 1646
1728 12.36 0
0
vec vec comp
dyn init dyn
init
929 20.08 1.07 10.7 3308 13.4
476143 2727 10.12 4.17 41.9 19635 78.7 51.7
4508 6.37 49.2 4489 71.3
s15850 182673 121525 2417 50.28 447 22.6 2782 3583 3391
s35932 69 850.1 18.2 1.35 1092 9.97 8.43
s38417 598062 1138194 1138194 15658 72.69 1114 501 1017 15471 0
s38584 3484 26.48 18.3 31.5 22533 282 250 334922 3842 87.17 188 35 3384 1281 1464
18.49 585
32348 1188183616 20625 19320 598062
21783 27603 21363 18656 28696
278 78.36 6.4 4.2 16423 15.7 14.3
cpu(s) cpu(s)
182673 7557 24.17 478 82.8 26960 5813 7874 27603
21389 18656 28696
21783
92239 92239
45198 21928 59854
58657 45198 21928 59854 476143 121525 58657
334922 137.4
s298 s344 s349 s382 s386 s400 s420 s444 s510 s526 s641 s713 s820 s832 s838 s953 s1196 s1238 s1488 s1494
343 611 611 667 413 663 738 586 729 694 1979 1184 980 984 2018 2302 3581 3589 1875 1882
62/5.53 95/6.43 95/6.43 103/6.48
244/3.02 105/5.58
127/5.46 183/10.8 92/12.87
681/2.96
387/4.74 circuits
vec/comp
395/4.75 522/6.88 552/6.49 399/5.77 255/3.86 249/3.94 219/3.33 120/3.44 102/6.50
vec/comp 64/5.36 98/6.23
106/6.29 118/3.50 102/6.50 282/2.62 97/6.03 227/3.21 131/5.30 187/10.58
250/3.92
411/5.60 556/6.44
390/4.81 vec/comp 61 / 5.62 96 / 6.36 108/ 5.65 110/ 6.06 118/3.50 101/ 6.50
133/ 5.77 186/10.59 205/5.77 250/3.92 265/3.71
411/5.60 555/6.45 595/6.03
364 654 656 734 414 753 738 813 738 720 2270 4922 984 996 2018 2312 3759 3684 1916 1927
vec/comp 40 / 9.10 65 / 10.06 72 / 9.11 86 / 8.53 76 / 6.46 84/ 8.96 202 / 3.65 85 / 9.56 80 / 9.23 90 / 8.0 246/ 9.23 246/20.01 120 / 8.20 124/ 8.03 615/ 3.28 251/ 9.21 413/ 9.10 415/ 8.88 160/11.97 160/12.04
vec/comp 30/12.13 44/14.86 44/14.91 60/12.23 68/6.09 60/12.55 184/4.01 60/13.55 68/10.85 81/8.89 117/19.40 118/41.71 100/9.84 102/9.76 595/3.39 201/11.5 314/11.97 305/12.08 127/15.09 129/14.94
vec/comp 64/5.68 102/6.19
97/6.53 118/6.22 101/4.10 107/7.05 310/2.38 83/7.05
116/6.21 181/12.54
259/19.0 209/4.71 210/4.74
361/6.4 477/7.88 416/8.85 (conj.)
SPC
paths enrich [14] Neat [11] paths Neat [11]
robust
(conj.) SPC (disconj.)
SPC non−robust
