[PDF] Top 20 J128 e IEICE 2006 6 最近の更新履歴 Hideo Fujiwara J128 e IEICE 2006 6

... In this table, compared with the conventional full scan test, when N = 2, N = 3 and N = 4, the average power is re- duced up to 61.8%, 72.7% and 75.6% respectively. The peak power dissipation is also reduced ... 完全なドキュメントを参照

... 4.2 Overview The aim of this algorithm is to find the minimum number of levels of cliques. Since the problem is NP- hard, we use a heuristic algorithm shown in Fig. 7. We first construct the compatibility graph G with ... 完全なドキュメントを参照

... {chiaye-o,fujiwara}@is.naist.jp Abstract—This paper introduces a new class of sequential circuits called acyclically testable sequential circuits which is wider than the class of acyclic sequential circuits but ... 完全なドキュメントを参照

... Fig. 11. Buffer size vs. TAT For d695 (Table II), our approach proves to be highly effective, even for the same bus frequency as [6], [7], at all power levels for bus widths ranging from 32 to 80 bits. For 96-bit ... 完全なドキュメントを参照

... Delete po from PO if the path list P(po) has been empty.[r] ... 完全なドキュメントを参照

... † E–mail:{masato-n, ohtake, kounoe, fujiwara}@is.naist.jp Abstract In this paper, we propose a design for testability method for test programs of software-based self-test using test program templates. ... 完全なドキュメントを参照

... All pseudo-primary inputs (PPIs) corresponding t o the same scan flip-flop group are merged into a single PPI. As shown in Figure 1, each of the primary inputs shares the s[r] ... 完全なドキュメントを参照

... Motion estimation (ME) is the process of identifying the best reference sample for a given macroblock. It is possible to perform ME by calculating the difference from every pos- sible reference sample and choosing the ... 完全なドキュメントを参照

... reports on some experimental results for our proposed method. Section 6 concludes with a brief summary. 2. Scan Tree Architecture Scan tree architectures group the compatible scan flip-flops in the same level so ... 完全なドキュメントを参照

... Example: Figure 3 shows an FSM timing test generation graph that is generated from the state- observable FSM shown in Fig. 2 and a two-pattern test set, which can detect all detectable path delay faults on the transition ... 完全なドキュメントを参照

... We compare the results with full scan circuits and partial scan circuits. The partial scan technique in this text means the scan technique that breaks the minimum flip-flops of the feedback in the circuit. Table 1 ... 完全なドキュメントを参照

... We plot the total testing time including tester loading time using equations deduced in Section 4. The parame- ters reflect the experimental circuit shown in Table 1. Fig.5 shows the Step1, Step2 and total testing time as ... 完全なドキュメントを参照

... Email:{hiroyu-i,yoneda,fujiwara}@is.naist.jp Abstract This paper presents a non-scan design-for-testability (DFT) method that guarantees complete fault efficiency (FE) for register transfer level (RTL) circuits. We ... 完全なドキュメントを参照

... The method first constructs a weighted directed system graph whose vertices are the cores and fanout points of functional interconnects in the SoC and whose edges are functional interconnects between the cores. The weight ... 完全なドキュメントを参照

... type3 の制御経路，観測経路を用いることによ り， M に 属するすべての組合せ 回路要素を 同時にテ ストできる．このテ ストの間，制御経路及び 観測経路 に 現れ る制御信号（ テストプ ラン ）を固定し ておくこ とができる．つまり，一つのテ スト セッション M に 対し て ，一つの 制御パターン を 与えれば ，連続クロッ クでテ スト ... 完全なドキュメントを参照

... Table 6: Test compression and Constraint RS spective test sets. As discussed above, the amount of test data is reduced from 2N + 2F to 2N + F if a TP has at least one functional instance. Otherwise, FUJISAN does ... 完全なドキュメントを参照

... ISB-RISC に 対し ， C ∗ (S) を 用いた テ スト 生成では ， S に 比べ，より多くの故障が 検出可能となり，テスト 生成時間もそれぞ れ 約 1/10000 ， 1/20 と 大幅に 短縮 した ．また ， C ∗ (S) で判定不可能となる故障も存在す るが ， S と比べてより多くの故障が 検出可能または冗 長と 判定され た ．すなわ ち，組合せ ATPG を用いて テスト ... 完全なドキュメントを参照

... Fig.2 Parallel connection of memories Serial connection allows memories with the same bit width to be connected. Figure 3 shows an example of four serially connected 8x32 word memories. In this example, the four memories ... 完全なドキュメントを参照

... Each Domino AND cell is composed of 6 transistors: two signal NMOS (named Na and Nb in the central gate, Fig. 2), one precharge PMOS (Ppr) and one evaluation NMOS (Nev), and two complementary transistors forming a ... 完全なドキュメントを参照

... 1. cycle(r test i )/f c test i is maximized (8) 2. m c i > 1 (9) 3. P max ≥ P 0 − power(c i ){1/m c i + 1/(m c i − 1)}(10) 4. P max /2 ≥ power(c i )/(m c i − 1) (11) If there exists such a core c i , we update m c i ... 完全なドキュメントを参照