[PDF] Top 20 J137 e IEICE 2007 8 最近の更新履歴 Hideo Fujiwara J137 e IEICE 2007 8

... Ikoma-shi, 630–0101 Japan. a) E-mail: [email protected] DOI: 10.1093/ietisy/e90–d.8.1202 SAF, which is representative of static faults, path delay fault (PDF) model need to be considered to ensure the ... 完全なドキュメントを参照

... To reduce the over-testing, first, untestable paths in an original circuit should be identified. Then the information about the untestable paths should be propagated to the ac- tual test environment, that is, the paths ... 完全なドキュメントを参照

... son Cases 2 and 3, we can observe the effect of considering both the core-level cost for transparency and the system- level cost for additional interconnect area simultaneously. In these results, we did not show the case ... 完全なドキュメントを参照

... 5. Optimization of the NoC Wrappers Parallel core tests are performed according to an optimum test schedule under constraints. Figure 8 shows an example of a bin-packing optimization [2, 3], where a rectangle ... 完全なドキュメントを参照

... Then we show that if an application of a sequential circuit to be loaded into an FPGA is inphase structure, all the path delay faults can be robustly tested with d + 2 cycles where d is [r] ... 完全なドキュメントを参照

... {hiroyu-i,yoneda,fujiwara}@is.naist.jp ABSTRACT This paper presents a non-scan design-for-testability method for register transfer level circuits. We first introduce a new testability of RTL circuits called ... 完全なドキュメントを参照

... {yoneda, fujiwara}@is.naist.jp Abstract This paper presents a stage-based test scheduling for memory cores with BISR scheme under power constraint. We introduce a model to compute the expected test time for a ... 完全なドキュメントを参照

... de-multiplexing and multiplexing interface circuits (DMIC- MIC) which performs bandwidth matching and test data flow-control between the external TAM and the internal virtual test bus lines. The scan control circuitry ... 完全なドキュメントを参照

... E-mail: ohtake, fujiwara @is.naist.jp Abstract — This paper proposes an approach to non-robust and functionally sensitizable path delay test generation through stuck- at test generation. In this approach, to ... 完全なドキュメントを参照

... CLB 5 of S 1 t 1 , t 2 and t 3 . Accordingly, R3 and R4 can be justified from PI 3, and can be observed at PO1. In other words, the path with thrus can be considered to be a scan path of R3 and R4, and consequently the ... 完全なドキュメントを参照

... VLSI design methodologies using hardware description languages have recently been adopted to reduce VLSI design time. VLSIs are designed at the Register Transfer Level (RTL), and RTL circuits consist of a data path part ... 完全なドキュメントを参照

... ∗ This research is supported in part by LA BORSF Research Competitive Subprogram. move from traditional shared-resource ATE architecture to new multi-port ATE architecture (such as Agilent 93000 series [1]) allows that ... 完全なドキュメントを参照

... M の 出力端子から RA まで の観測経路を単一の制御信号からなるテストプ ランで 実現する経路とし て， type1 に加え ， type2 ， type3 の 経路も新たに 考え る（ 図 2 ） ．三つの タ イプ の 経路に よって ，各組合せ 回路要素の異な る入力端子に TPG で 発生し た異なるテ スト パターン ... 完全なドキュメントを参照

... Chikateru JINNO †∗ , Michiko INOUE † , and Hideo FUJIWARA † あら まし 本論文では ，ホールド と スイッチの機能を考慮し て ，内部平衡構造を拡張し た順序回路のクラスで ある内部切換平衡構造を提案する．提案するクラスは ，組合せテ スト 生成複雑度でテ スト 生成可能であり，平衡 ... 完全なドキュメントを参照

... 縮退故障のテスト生成アルゴリズムを用いたパス遅延故障に対する テスト生成法 大谷 浩平 † 大竹 哲史 †† 藤原 秀雄 †† A Test Generation Method for Path Delay Faults Using Stuck-at Fault Test Generation Algorithms ... 完全なドキュメントを参照

... ログラムテンプレートとは，オペランドの値が未決定 のテストプログラムであり，テスト対象モジュールに 対し，テストパターンの正当化及びテスト応答の観測 を行う命令列からなる．この手法では，テンプレート に 対 し ，い く つ か の ラ ン ダ ム パ タ ー ン を オ ペ ラ ン ド に与えたシミュレーション結果から回帰解析により制 ... 完全なドキュメントを参照

... keywords: system-on-a-chip, test scheduling, reconfig- urable union wrapper, test access mechanism 1 Introduction In the SoC test environment, each embedded core is iso- lated from other logics during test of the core. ... 完全なドキュメントを参照

... keep a list to record the set of single stuck-at faults that propagate to itself. We would like to propose a backward fault simulation procedure without any redundant work as introduced in Figure 8. The new ... 完全なドキュメントを参照

... The experiments were done using three SoCs from the ITC’02 SoC Benchmark suite [8], d695, p22810, and p93791. For thermal simulation, cycle-accurate power profiles provided by the authors of [7] were used. Note ... 完全なドキュメントを参照

... I. I NTRODUCTION Path delay faults can detect many defects that escape detec- tion by test sets that target only single stuck-at fault tests [?]. The detection of a path delay fault requires the application of pairs of ... 完全なドキュメントを参照