[PDF] Top 20 C213 2010 1 DELTA 最近の更新履歴 Hideo Fujiwara

... Figure 1. The false path identification flow. In this paper, we focus on path mapping from a set of RTL false paths to gate level paths without considering MIP-LS. Figure 1 shows the false path identification ... 完全なドキュメントを参照

... IV. E XPERIMENTAL R ESULTS In the experiments, we evaluate the effectiveness of the method. We used RTL circuits synthesized from behavioral level benchmark circuits, 3rd Lattice Wave Filter (LWF), Tseng[16], Paulin[17] ... 完全なドキュメントを参照

... Several scan architectures based on multiple internal scan chain design have been proposed to reduce test data volume and test application time. The method in [1] effectively reduces test data volume and test ... 完全なドキュメントを参照

... sum of the output. For the classes of LFSR and I 2 LFSR, any k-stage LFSR and I 2 LFSR can be modified to be SR- equivalent by manipulating the linear sum of the input. To illustrate an example, consider a k-stage I 2 LF ... 完全なドキュメントを参照

... set of RTL paths so that listing mapped gate level signal lines through which the gate level paths pass. Note that, in the original procedure of 1), multiple paths which have the same starting and ending points ... 完全なドキュメントを参照

... Fig. 1. SDQL and selection method for b19. Fig. 2. SDQL and base test set for b19. from T base based on transition fault coverage (coverage based). We used TetraMAX(Synopsys) and SunFireX4100 (3.0GHz CPU and 16GB ... 完全なドキュメントを参照

... Fig. 1. Two-frame version of full scan circuit. possibility to reduce over-testing, which is a result of scan methods that allow generation of scan patterns that are illegal during functional mode. Although this ... 完全なドキュメントを参照

... In this work, our motivation is to target unmodeled defects. Therefore, one of our core objectives is to propagate transi- tions through as many paths in the design as possible. Let us first define the concept of ... 完全なドキュメントを参照

... key words: false path, high level testing, path mapping, functional equiv- alence 1. Introduction For circuit design and testing, false path information is very valuable since it can be used for reducing circuit ... 完全なドキュメントを参照

... Fig. 1 a Architecture of the Parwan processor; b Dataflow graph of the Parwan processor (only the registers are shown) cone, it will affect and be affected by many lines and ... 完全なドキュメントを参照

... 2. Related Work In [23], single-cycle transparency is achieved by embed- ding multiplexers in the behavioral models described using a hardware description language. An example is shown in Fig. 1. An additional ... 完全なドキュメントを参照

... 3(b), by adding an XOR at the output with inputs from y 3 and y 2 that is indicated by the broken line arrow, the output assignment of the modified LF 2 SR becomes the same as that of the shift register of Figure ... 完全なドキュメントを参照

... 1. Introduction In order to increase the testability of a circuit, design for testability (DFT) is the most popular approach. Scan design is the mainstream technique used today because it effectively addresses the ... 完全なドキュメントを参照

... The most important merit of full scan-based DFT methods for asynchronous circuits is that the well developed combi- national circuit testing can be applied with minor modifica- tion. The L1L2* scan designs [5], [6] ... 完全なドキュメントを参照

... fault and a slow-to-fall fault. It is assumed that in the fault- free circuit each signal line has some nominal delay. Delay faults result in an increase of this delay. Under the transi- tion fault model, the extra delay ... 完全なドキュメントを参照

... Science City, 630-0192 Japan. *{norlina,ooichiayee,zuri}@fke.utm.my, +fujiwara@is.naist.jp ABSTRACT This paper introduces a new class of assignment decision diagrams (ADD) called thru-testable ADDs based on a ... 完全なドキュメントを参照

... Level n. The number of danger levels can be decided according to the number of LCP levels. To be able to give the TPSs in the higher level danger tables more chances to be applied, the periodic counters are used. The ... 完全なドキュメントを参照

... Part 1 to find a Hamiltonian cycle which consume less peak power from the constructed complete graph and Part 2 to find a Hamiltonian path having lower peak power from Hamiltonian ...Part 1 of algorithm ... 完全なドキュメントを参照

... R 1 shown in Figure 7(a). R 1 is a scan-testable LF 2 ...R 1 . However, if we don’t use FF y 1 in R 1 for normal function, ...y 1 and the kernel, no differential value can be ... 完全なドキュメントを参照

... Most of the previous approaches are aimed at average power reduction, however they have also achieved some re- duction in peak power as a by-product [1, 11, 9, 16, 14, 17]. The approach by Chou et al. [1] ... 完全なドキュメントを参照