[PDF] Top 20 C64 2000 12 ATS 最近の更新履歴 Hideo Fujiwara

... In case that both these heuristics cannot justify or prove unjustifiable the sensitized propagation path, the backward justification performs heuristics BJ1* and BJ2* [r] ... 完全なドキュメントを参照

... Given a scheduled data flow graph and a module assignment, we assign variables to registers, such that the area overhead required for a strongly self-testable data pat[r] ... 完全なドキュメントを参照

... One of our future works is to introduce concurrent BIST to reduce test application time. Acknowledgments This work was supported in part by Semiconductor Tech- nology Academic Research Center (STARC) under the Re- search ... 完全なドキュメントを参照

... Theorem 1[3] If a sequential circuit S is an internally balanced structure, S allows test generation with combinational test generation complexity. However, each fault on a separable primary input x in S corresponds to a ... 完全なドキュメントを参照

... 1 のプロトコルが提案されていた（ n:プロセッサ数） ．本論文では ，同期時 間 12n の無待機時計合せプ ロトコルを提案する．また，無待機時計合せプロトコルの同期時間の下界が n − 1 であることを証明し ，本論文で提案するプ ロト コルが 同期時間に 関し てオーダ 的に ... 完全なドキュメントを参照

... In this paper, we present a new non-scan DFT method for controller circuits of VLSIs which guaran- tees complete fault efficiency. In general, a controller valid states. Moreover, in order to observe responses of the ... 完全なドキュメントを参照

... S832 23 996 1012 23 86.7 12.5 S1488 14 1916 1924 12 91.7 11.11 S1494 14 1926 1952 11 90.8 12.79 In Table 1, we report the results obtained for config- urable LFSR-based TPG synthesis. For each ... 完全なドキュメントを参照

... plans at RTL, where a test plan is a control sequence to prop- agate test patterns from the primary inputs to the inputs of the respective hardware elements and to propagate responses from the output of the respective ... 完全なドキュメントを参照

... 36 Consider SR-equivalent circuit C 2 . If we assign 8 flip-flops from FF1 to FF8 to the secret register, the contents of the secret register appear at the output because OUT@15 = FF1@0, OUT@14 = FF2@0, OUT@13 = FF3@0, ... 完全なドキュメントを参照

... sale, Jerry is willing to pay no more than $1000. The second kind of equilibrium features t·ade of both the lemon and the peach. That is, Jerry selects T and Freddie plays the strategy TPTL. In order for this equilibrium ... 完全なドキュメントを参照

... ，もと の演算間の経路は共有し た演算器を通るループ となる． よって ，その演算間の経路上にあるいずれかの変数は ループ を切断するための スキャンレジ スタに 割り当て なければ なら ない ．両立可能な 演算間の 経 路の 長さ ， すなわちその経路上にある変数の数が 大きければ ，そ の うちいずれか ... 完全なドキュメントを参照

... • More test resources are given to the upper layer (i.e. layer 2) in order to increase the scheduling flexibility, which would result in a more thermal-efficient test schedule. This is based on our earlier observation on ... 完全なドキュメントを参照

... In a reliable broadcast model, if and only if some process broadcasts an update message in a write operation execution, all correct processes receive the update message.. This does not d[r] ... 完全なドキュメントを参照

... It is shown that sequential circuits can be classified by their structure as follows: {sequential circuits of acyclic structure} ⊃ {sequential circuits of internally balanced structur[r] ... 完全なドキュメントを参照

... は ，核回路が 組合せ回路となるので 組合せ回路用のテ スト 生成アルゴ リズムでテ スト 生成が 可能（ 以下，組 † 奈良先端科学技術大学院大学情報科学研究科，生駒市 Graduate School of Information Science, Nara Institute of Science and Technology, Ikoma-shi, 630–0101 Japan †† ... 完全なドキュメントを参照

... On the other hand, in the partial scan design based on balanced structure, the minimum number of scan registers is five, e.g., the set of registers to be scanned is {b,c,e, f , k}. When the kernel is made an ... 完全なドキュメントを参照

... Many indirect implications can be easily derived during static learning, while high level recursive learning has to be applied to find them during branch and bound search2[r] ... 完全なドキュメントを参照

... The hierarchical test generation of a data path consists of the fol- lowing two steps: for individual combinational hardware el- ements, generate test patterns at gate level and generate[r] ... 完全なドキュメントを参照

... International Test Conference, pp.[r] ... 完全なドキュメントを参照

... Control Forest(stage 1): The path used for propagating any test patterns, from a primary input to the input port of a hardware element, is called a control path to the port.. On reducing[r] ... 完全なドキュメントを参照