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[PDF] Top 20 C212 2010 1 ASPDAC 最近の更新履歴 Hideo Fujiwara

Has 10000 "C212 2010 1 ASPDAC 最近の更新履歴 Hideo Fujiwara" found on our website. Below are the top 20 most common "C212 2010 1 ASPDAC 最近の更新履歴 Hideo Fujiwara".

C212 2010 1 ASPDAC 最近の更新履歴  Hideo Fujiwara

C212 2010 1 ASPDAC 最近の更新履歴 Hideo Fujiwara

... R 1 shown in Figure 7(a). R 1 is a scan-testable LF 2 ...R 1 . However, if we don’t use FF y 1 in R 1 for normal function, ...y 1 and the kernel, no differential value can be ... 完全なドキュメントを参照

6

C214 2010 3 DTIS 最近の更新履歴  Hideo Fujiwara

C214 2010 3 DTIS 最近の更新履歴 Hideo Fujiwara

... IV. E XPERIMENTAL R ESULTS In the experiments, we evaluate the effectiveness of the method. We used RTL circuits synthesized from behavioral level benchmark circuits, 3rd Lattice Wave Filter (LWF), Tseng[16], Paulin[17] ... 完全なドキュメントを参照

6

C227 2010 12 ATS 最近の更新履歴  Hideo Fujiwara

C227 2010 12 ATS 最近の更新履歴 Hideo Fujiwara

... Several scan architectures based on multiple internal scan chain design have been proposed to reduce test data volume and test application time. The method in [1] effectively reduces test data volume and test ... 完全なドキュメントを参照

4

C228 2010 12 WRTLT 最近の更新履歴  Hideo Fujiwara

C228 2010 12 WRTLT 最近の更新履歴 Hideo Fujiwara

... sum of the output. For the classes of LFSR and I 2 LFSR, any k-stage LFSR and I 2 LFSR can be modified to be SR- equivalent by manipulating the linear sum of the input. To illustrate an example, consider a k-stage I 2 LF ... 完全なドキュメントを参照

6

C216 2010 4 DDECS 最近の更新履歴  Hideo Fujiwara

C216 2010 4 DDECS 最近の更新履歴 Hideo Fujiwara

... set of RTL paths so that listing mapped gate level signal lines through which the gate level paths pass. Note that, in the original procedure of 1), multiple paths which have the same starting and ending points ... 完全なドキュメントを参照

4

C219 2010 5 ETS 最近の更新履歴  Hideo Fujiwara

C219 2010 5 ETS 最近の更新履歴 Hideo Fujiwara

... Fig. 1. SDQL and selection method for b19. Fig. 2. SDQL and base test set for b19. from T base based on transition fault coverage (coverage based). We used TetraMAX(Synopsys) and SunFireX4100 (3.0GHz CPU and 16GB ... 完全なドキュメントを参照

1

C222 2010 10 ISCIT 最近の更新履歴  Hideo Fujiwara

C222 2010 10 ISCIT 最近の更新履歴 Hideo Fujiwara

... Fig. 1. Two-frame version of full scan circuit. possibility to reduce over-testing, which is a result of scan methods that allow generation of scan patterns that are illegal during functional mode. Although this ... 完全なドキュメントを参照

6

C224 2010 11 ITC 最近の更新履歴  Hideo Fujiwara

C224 2010 11 ITC 最近の更新履歴 Hideo Fujiwara

... modes applied (TM) by the proposed method in Columns 2, 3, and 4, respectively. The column heading Original indicates the case when the original functional test sequence is applied on a given design, whereas the column ... 完全なドキュメントを参照

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C225 2010 12 ATS 最近の更新履歴  Hideo Fujiwara

C225 2010 12 ATS 最近の更新履歴 Hideo Fujiwara

... Theorem 1: For an asynchronous circuit C, the combina- tional part of C can be completely tested if C is BF-scan testable. Proof: Let C1, C2, L1 and L2 be sub circuits and sets of sequential elements ... 完全なドキュメントを参照

7

J153 e IEICE 2010 7 最近の更新履歴  Hideo Fujiwara J153 e IEICE 2010 7

J153 e IEICE 2010 7 最近の更新履歴 Hideo Fujiwara J153 e IEICE 2010 7

... key words: false path, high level testing, path mapping, functional equiv- alence 1. Introduction For circuit design and testing, false path information is very valuable since it can be used for reducing circuit ... 完全なドキュメントを参照

9

J151 e JETTA 2010 4 最近の更新履歴  Hideo Fujiwara J151 e JETTA 2010 4

J151 e JETTA 2010 4 最近の更新履歴 Hideo Fujiwara J151 e JETTA 2010 4

... Fig. 1 a Architecture of the Parwan processor; b Dataflow graph of the Parwan processor (only the registers are shown) cone, it will affect and be affected by many lines and ... 完全なドキュメントを参照

14

J152 e IEICE 2010 6 最近の更新履歴  Hideo Fujiwara J152 e IEICE 2010 6

J152 e IEICE 2010 6 最近の更新履歴 Hideo Fujiwara J152 e IEICE 2010 6

... 2. Related Work In [23], single-cycle transparency is achieved by embed- ding multiplexers in the behavioral models described using a hardware description language. An example is shown in Fig. 1. An additional ... 完全なドキュメントを参照

11

C215 2010 4 DDECS 最近の更新履歴  Hideo Fujiwara

C215 2010 4 DDECS 最近の更新履歴 Hideo Fujiwara

... 3(b), by adding an XOR at the output with inputs from y 3 and y 2 that is indicated by the broken line arrow, the output assignment of the modified LF 2 SR becomes the same as that of the shift register of Figure ... 完全なドキュメントを参照

4

C223 2010 11 ITC 最近の更新履歴  Hideo Fujiwara

C223 2010 11 ITC 最近の更新履歴 Hideo Fujiwara

... 1. Introduction In order to increase the testability of a circuit, design for testability (DFT) is the most popular approach. Scan design is the mainstream technique used today because it effectively addresses the ... 完全なドキュメントを参照

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J154 e MJCS 2010 1 最近の更新履歴  Hideo Fujiwara J154 e MJCS 2010 1

J154 e MJCS 2010 1 最近の更新履歴 Hideo Fujiwara J154 e MJCS 2010 1

... Table 1 presents the characteristic of the benchmark ...Table 1, #FF represents the number of flip-flops while PI/PO represents the number of inputs/outputs of the ... 完全なドキュメントを参照

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C221 2010 7 IOLTS 最近の更新履歴  Hideo Fujiwara

C221 2010 7 IOLTS 最近の更新履歴 Hideo Fujiwara

... Some examples of the TPS movements are also shown in Fig. 7. According to the result of an aging analysis, a TPS can move from the scheduling table to the first level danger table like the TPS 9, but can jump to a two or ... 完全なドキュメントを参照

6

J150 e IEICE 2010 1 最近の更新履歴  Hideo Fujiwara J150 e IEICE 2010 1

J150 e IEICE 2010 1 最近の更新履歴 Hideo Fujiwara J150 e IEICE 2010 1

... A bridging fault is a fault model that expresses a short be- tween signal lines. Bridging faults are classified into AND type and OR type based on failure behavior. It is necessary to generate a test pattern that detects ... 完全なドキュメントを参照

9

C213 2010 1 DELTA 最近の更新履歴  Hideo Fujiwara

C213 2010 1 DELTA 最近の更新履歴 Hideo Fujiwara

... Figure 1. The false path identification flow. In this paper, we focus on path mapping from a set of RTL false paths to gate level paths without considering MIP-LS. Figure 1 shows the false path identification ... 完全なドキュメントを参照

6

C218 2010 5 ETS 最近の更新履歴  Hideo Fujiwara

C218 2010 5 ETS 最近の更新履歴 Hideo Fujiwara

... In this work we have focused on the problem of peak power consumption during test-cycle for at-speed testing. The method- ology proposed in this work is based on scan cells reordering. Many direction has been explored to ... 完全なドキュメントを参照

1

C231 2010 12 APCCAS 最近の更新履歴  Hideo Fujiwara

C231 2010 12 APCCAS 最近の更新履歴 Hideo Fujiwara

... Applying the same test schedule for both chip layers simultaneously results in the temperature profile of core 5— the hottest core in the design—shown in Figure 7. The maximum temperature is approximately 116 °C. In ... 完全なドキュメントを参照

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