NTPF082N65S3F MOSFET – Power, N-Channel, SUPERFET III, FRFET

MOSFET – Power, N-Channel, SUPERFET III, FRFET

650 V, 40 A, 82 mW

Description

SUPERFET III MOSFET is ON Semiconductor’s brand-new high voltage super-junction (SJ) MOSFET family that is utilizing charge balance technology for outstanding low on-resistance and lower gate charge performance. This advanced technology is tailored to minimize conduction loss, provide superior switching performance, and withstand extreme dv/dt rate.

Consequently, SUPERFET III MOSFET is very suitable for the various power system for miniaturization and higher efficiency.

SUPERFET III FRFET MOSFET’s optimized reverse recovery performance of body diode can remove additional component and improve system reliability.

Features

• ^{700 V @ T}

= 150 ° C

• ^{Typ. R}

= 70 m W

• Ultra Low Gate Charge (Typ. Q

= 70 nC)

• Low Effective Output Capacitance (Typ. C

= 680 pF)

• 100% Avalanche Tested

• These Devices are Pb−Free and are RoHS Compliant

• Telecom/Sever Power Supplies

• Industrial Power Supplies

• UPS/Solar

TO−220 FULLPAK CASE 221D www.onsemi.com

D

S G

GD S

MARKING DIAGAM

$Y = ON Semiconductor Logo

&Z = Assembly Plant Code

$Y&Z&3&K NTPF 082N65S3F

V_DS R_DS(ON) MAX I_D MAX

650 V 82 mW @ 10 V 40 A

ABSOLUTE MAXIMUM RATINGS (T_C = 25°C, Unless otherwise specified)

Symbol Parameter Value Unit

VDSS Drain to Source Voltage 650 V

V_GSS Gate to Source Voltage DC ±30 V

AC (f > 1 Hz) ±30 V

I_D Drain Current Continuous (TC = 25°C) 40* A

Continuous (TC = 100°C) 25.5*

I_DM Drain Current Pulsed (Note 1) 100* A

EAS Single Pulsed Avalanche Energy (Note 2) 510 mJ

I_AS Avalanche Current (Note 2) 4.8 A

EAR Repetitive Avalanche Energy (Note 1) 0.48 mJ

dv/dt MOSFET dv/dt 100 V/ns

Peak Diode Recovery dv/dt (Note 3) 50

PD Power Dissipation (T_C = 25°C) 48 W

Derate Above 25°C 0.38 W/°C

T_J, T_STG Operating and Storage Temperature Range −55 to +150 °C

T_L Maximum Lead Temperature for Soldering, 1/8″ from Case for 5 s 300 °C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

*Drain current limited by maximum junction temperature.

1. Repetitive rating: pulse-width limited by maximum junction temperature.

2. I_AS = 4.8 A, R_G = 25W, starting T_J = 25°C.

3. I_SD ≤ 20 A, di/dt ≤ 200 A/ms, VDD ≤ 400 V, starting TJ = 25°C.

THERMAL CHARACTERISTICS

Symbol Parameter Value Unit

R_qJC Thermal Resistance, Junction to Case, Max. 2.62 _C/W

R_qJA Thermal Resistance, Junction to Ambient, Max. 62.5

PACKAGE MARKING AND ORDERING INFORMATION

Part Number Top Marking Package Packing Method Quantity

NTPF082N65S3F NTPF082N65S3F TO−220 FULLPACK

(Pb−Free) Tube 50 Units

ELECTRICAL CHARACTERISTICS (T_C = 25°C unless otherwise noted)

Symbol Parameter Test Conditions Min Typ Max Unit

OFF CHARACTERISTICS

BVDSS Drain to Source Breakdown Voltage V_GS= 0 V, I_D= 1 mA, T_J= 25_C 650 − − V

V_GS= 0 V, I_D= 1 mA, T_J= 150_C 700 − − V

DBVDSS/DTJ Breakdown Voltage Temperature

Coefficient I_D= 10 mA, Referenced to 25_C − 0.67 − V/_C

I_DSS Zero Gate Voltage Drain Current V_DS= 650 V, V_GS= 0 V − − 10 mA

V_DS= 520 V, T_C= 125_C − 97 −

I_GSS Gate to Body Leakage Current V_GS=±30 V, V_DS= 0 V − − ±100 nA

ON CHARACTERISTICS

V_GS(th) Gate Threshold Voltage V_GS= V_DS, I_D= 0.97 mA 3.0 − 5.0 V

R_DS(on) Static Drain to Source On Resistance V_GS= 10 V, I_D= 20 A − 70 82 mW

g_FS Forward Transconductance V_DS= 20 V, I_D= 20 A − 24 − S

DYNAMIC CHARACTERISTICS

C_iss Input Capacitance V_DS= 400 V, V_GS= 0 V, f = 1 MHz − 3240 − pF

C_oss Output Capacitance − 70 − pF

Coss(eff.) Effective Output Capacitance VDS= 0 V to 400 V, VGS= 0 V − 680 − pF

Coss(er.) Energy Related Output Capacitance VDS= 0 V to 400 V, VGS= 0 V − 125 − pF

Qg(tot) Total Gate Charge at 10 V V_DS= 400 V, I_D= 20 A, V_GS= 10 V

(Note 4) − 70 − nC

Qgs Gate to Source Gate Charge − 24 − nC

Qgd Gate to Drain “Miller” Charge − 27 − nC

ESR Equivalent Series Resistance f = 1 MHz − 2.3 − W

SWITCHING CHARACTERISTICS

td(on) Turn-On Delay Time VDD= 400 V, ID= 20 A,

V_GS= 10 V, R_g= 3W (Note 4)

− 30 − ns

tr Turn-On Rise Time − 27 − ns

td(off) Turn-Off Delay Time − 64 − ns

tf Turn-Off Fall Time − 3.7 − ns

SOURCE-DRAIN DIODE CHARACTERISTICS

I_S Maximum Continuous Source to Drain Diode Forward Current − − 40 A

I_SM Maximum Pulsed Source to Drain Diode Forward Current − − 100 A

V_SD Source to Drain Diode Forward

Voltage V_GS= 0 V, I_SD= 20 A − − 1.3 V

t_rr Reverse Recovery Time V_GS= 0 V, I_SD= 20 A,

dIF/dt = 100 A/ms − 103 − ns

Q_rr Reverse Recovery Charge − 397 − nC

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

4. Essentially independent of operating temperature typical characteristics.

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics

Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage

Figure 4. Body Diode Forward Voltage Variation vs. Source Current and Temperature

VDS, Drain-Source Voltage [V]

ID, Drain Current [A]

0.10.2

* Notes:

1. 250 ms Pulse Test 2. TC = 25°C VGS = 10.0V

8.0 V 7.0 V 6.5 V 6.0 V 5.5 V

1 10

1 10 100 200

VGS, Gate-Source Voltage [V]

ID, Drain Current [A]

13 10 100 200

4 5 6 7 8 9

150°C

25°C

−55°C

* Notes:

1. VDS = 20 V 2. 250 ms Pulse Test

ID, Drain Current [A]

RDS(ON), Drain-Source On-Resistance [W]

0.000 0.05 0.20

20 40 60 80 100

VGS = 10 V

* Note: TC = 25°C

VGS = 20 V 0.10

0.15

VSD, Body Diode Forward Voltage [V]

IS, Reverse Drain Current [A]

0.0010.0 0.01 1000

0.5 1.0 1.5 2.0

150°C

* Notes:

1. VGS = 0 V 2. 250 ms Pulse Test

0.1 1 10 100

25°C

−55°C

oltage [V]

10 * Note: I_D = 20 A

4 6

8 _{VDS = 130 V}

VDS = 400 V 100000

* Notes:

100 1000 10000

C_oss C_iss

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 7. Breakdown Voltage Variation

vs. Temperature Figure 8. On-Resistance Variant vs. Temperature

Figure 9. Maximum Safe Operation Area Figure 10. Maximum Drain Current vs. Case Temperature

TJ, Junction Temperature [5C]

BVDSS, [Normalized] Drain-Source Breakdown Voltage 0.8 0.9 1.2

−50 0 50 150

* Notes:

1. VGS = 0 V 2. ID = 10 mA

1.0 1.1

100

TJ, Junction Temperature [5C]

RDS(on), [Normalized] Drain-Source On-Resistance

0.0 0.5 3.0

−50 0 50 150

* Notes:

1. VGS = 10 V 2. ID = 20 A

1.0 1.5

100 2.0

2.5

TC, Case Temperature [5C]

ID, Drain Current [A]

0 10

25 50 75 125 150

20 30 40 50

100

EOSS, [mJ]

4 8 12 16 20

VDS, Drain-Source Voltage [V]

ID, Drain Current [A]

0.011 10 100 1000

0.1 1 10 100 200

* Notes:

1. TJ = 25°C 2. TJ = 150°C 3. Single Pulse Operation in This Area is Limited by RDS(on)

10 ms 100 ms 1 ms 10 ms

DC

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 12. Transient Thermal Response Curve

SINGLE PULSE

DUTY CYCLE−DESCENDING ORDER

P_DM

t₁ t₂

t, Rectangular Pulse Duration (s) r(t), Normalized Effective Transient Thermal Resistance

0.001 0.01 0.1 1 2

10⁻⁴ 10⁻³ 10⁻² 10⁻¹ 10⁰ 10¹ 10²

Notes:

Z_qJC(t) = r(t) × RqJC R_qJC = 2.62°C/W

Peak TJ = PDM × ZqJC(t) + TC Duty Cycle, D = t1 / t2 D = 0.5

0.2 0.1 0.05 0.02 0.01

Figure 13. Gate Charge Test Circuit & Waveform

Figure 14. Resistive Switching Test Circuit & Waveforms

Figure 15. Unclamped Inductive Switching Test Circuit & Waveforms RL

V_DS VGS

VGS

RG

DUT

VDD

V_DS

V_GS10%

90%

10%

90% 90%

t_on t_off

t_r t_f

t_d(on) t_d(off)

Q_g Q_gd Q_gs

VGS

Charge V_DS

V_GS

R_L

DUT IG = Const.

V_DD VDS

R_G VGS DUT

L

ID

tp

V_DD

t_p Time

IAS

BV_DSS

I_D(t)

V_DS(t) E_AS+1

2@LI_AS²

DUT

L

V_DD R_G

I_SD

V_SD +

−

V_GS

Same Type as DUT

− dv/dt controlled by R_G

− I_SD controlled by pulse period Driver

V_GS (Driver)

I_SD (DUT)

V_DS

(DUT) V_SD

IRM

10 V

di/dt

VDD

IFM, Body Diode Forward Current

Body Diode Reverse Current Body Diode Recovery dv/dt

Body Diode Forward Voltage Drop D+ Gate Pulse Width

Gate Pulse Period

TO−220 FULLPAK CASE 221D−03

ISSUE K

DATE 27 FEB 2009

STYLE 4:

PIN 1. CATHODE 2. ANODE 3. CATHODE STYLE 1:

PIN 1. GATE 2. DRAIN 3. SOURCE

STYLE 2:

PIN 1. BASE 2. COLLECTOR 3. EMITTER

STYLE 3:

PIN 1. ANODE 2. CATHODE 3. ANODE

DIM A

MIN MAX MIN MAX MILLIMETERS 0.617 0.635 15.67 16.12

INCHES

B 0.392 0.419 9.96 10.63 C 0.177 0.193 4.50 4.90 D 0.024 0.039 0.60 1.00 F 0.116 0.129 2.95 3.28

G 0.100 BSC 2.54 BSC

H 0.118 0.135 3.00 3.43 J 0.018 0.025 0.45 0.63 K 0.503 0.541 12.78 13.73 L 0.048 0.058 1.23 1.47

N 0.200 BSC 5.08 BSC

Q 0.122 0.138 3.10 3.50 R 0.099 0.117 2.51 2.96 S 0.092 0.113 2.34 2.87 U 0.239 0.271 6.06 6.88

STYLE 5:

PIN 1. CATHODE 2. ANODE 3. GATE

STYLE 6:

PIN 1. MT 1 2. MT 2 3. GATE

SEATING PLANE

−T−

U C

S

J R SCALE 1:1

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH 3. 221D-01 THRU 221D-02 OBSOLETE, NEW

STANDARD 221D-03.

MARKING DIAGRAMS

xxxxxx = Specific Device Code G = Pb−Free Package A = Assembly Location Y = Year

WW = Work Week xxxxxxG

AYWW

A = Assembly Location

Y = Year

WW = Work Week xxxxxx = Device Code G = Pb−Free Package AKA = Polarity Designator

AYWW xxxxxxG

AKA

Bipolar Rectifier

−B−

−Y−

G N D

L K

H A

F Q

3 PL 1 2 3

B M

0.25 (0.010)M Y

information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products