MOSFET - Power, Single N-Channel, D2PAK-7L

© Semiconductor Components Industries, LLC, 2020

May, 2022 − Rev. 0 1 Publication Order Number:

NVBG110N65S3F/D

MOSFET - Power, Single N-Channel, D2PAK-7L

650 V, 110 m W , 30 A

NVBG110N65S3F

Description

SUPERFET

III MOSFET is onsemi’s brand−new high voltage super−junction (SJ) MOSFET family that is utilizing charge balance technology for outstanding low on−resistance and lower gate charge performance. This advanced technology is tailored to minimize conduction loss, provide superior switching performance, and withstand extreme dv/dt rate.

Consequently, SUPERFET III MOSFET is very suitable for the various power system for miniaturization and higher efficiency.

SUPERFET III FRFET

MOSFET’s optimized reverse recovery performance of body diode can remove additional component and improve system reliability.

In addition, the D2PAK 7 lead package offers Kelvin sense. This allows higher switching speeds and gives designers the ability to reduce the overall application footprint.

Features

• ^{700 V @ T}

= 150 ° C

• ^{Typ. R}

= 93 m W

• Ultra Low Gate Charge (Typ. Q

= 58 nC)

• Low Effective Output Capacitance (Typ. C

= 553 pF)

• 100% Avalanche Tested

• AEC−Q101 Qualified and PPAP Capable

• These Devices are Pb−Free and are RoHS Compliant

• Automotive On Board Charger

• Automotive DC/DC Converter for BEV

See detailed ordering and shipping information on page 6 of this data sheet.

ORDERING INFORMATION V_(BR)DSS R_DS(ON) MAX I_D MAX

650 V 110 mW @ 10 V 30 A

D2PAK−7L CASE 418BJ

MARKING DIAGRAM N−CHANNEL MOSFET

Drain (TAB)

Power Source (Pins 3, 4, 5, 6, 7) Gate (Pin 1)

VBG110N65S3F = Specific Device Code A = Assembly Location

Y = Year WW = Work Week ZZ = Lot Traceability

VBG110 N65S3F AYWWZZ Driver Source (Pin 2)

Table 1. ABSOLUTE MAXIMUM RATINGS (T_C = 25°C unless otherwise stated)

Symbol Parameter Value Unit

VDSS Drain−to−Source Voltage 650 V

VGS Gate−to−Source Voltage − DC ±30 V

− AC (f > 1 Hz) ±30

ID Drain Current − Continuous (T_C = 25°C) 30 A

− Continuous (T_C = 100°C) 19.5

I_DM Drain Current − Pulsed (Note 1) 69 A

E_AS Single Pulse Avalanche Energy (Note 2) 380 mJ

I_AS Avalanche Current 3.5 A

E_AR Repeated Avalanche Energy (Note 1) 2.4 mJ

dv/dt MOSFET dv/dt 100 V/ns

Peak Diode Recovery dv/dt (Note 3) 50

P_D Power Dissipation T_C = 25°C 240 W

− Derate Above 25°C 1.92 W/°C

T_J, T_stg Operating Junction and Storage Temperature Range −55 to 150 °C

T_L Maximum Lead Temperature for Soldering, 1/8″ from Case for 5 Seconds 300 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

1. Repetitive rating: pulse*width limited by maximum junction temperature.

2. I_AS = 3.5 A, R_G = 25 W, starting T_J = 25°C.

3. I_SD ≤ 15 A, di/dt ≤ 200 A/ms, VDD ≤ 400 V, starting TC = 25°C.

Table 2. THERMAL RESISTANCE RATINGS

Symbol Parameter Max Unit

R_qJC Thermal Resistance, Junction−to−Case, Max. 0.52 °C/W

R_qJA Thermal Resistance, Junction−to−Ambient, Max. 40

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ELECTRICAL CHARACTERISTICS (T_C = 25°C unless otherwise noted)

Symbol Parameter Test Conditions Min Typ Max Unit

OFF CHARACTERISTICS

BVDSS Drain−to−Source Breakdown Voltage VGS= 0 V, ID= 1 mA, TJ= 25°C 650 − − V V_GS= 0 V, I_D= 10 mA, T_J= 150°C 700 − − V DBVDSS/DTJ Breakdown Voltage Temperature Coefficient I_D= 20 mA, Referenced to 25°C − 0.61 − V/°C

IDSS Zero Gate Voltage Drain Current V_DS= 650 V, V_DS= 0 V − − 10 mA

V_DS= 520 V, T_C= 125°C − 128 − mA

I_GSS Gate−to−Body Leakage Current V_GS= 0 V, I_D= 1 mA, T_J= 25°C − − ±100 nA ON CHARACTERISTICS

V_GS(th) Gate Threshold Voltage V_GS= V_DS, I_D = 0.74 mA 3.0 − 5.0 V

R_DS(on) Static Drain−to−Source On Resistance V_GS= 10 V, I_D= 15 A − 93 110 mW

g_FS Forward Transconductance V_GS= 20 V, I_D= 15 A − 17 − S

DYNAMIC CHARACTERISTICS

C_iss Input Capacitance V_DS= 400 V, V_GS= 0 V, f = 1 MHz − 2560 − pF

C_oss Output Capacitance − 50 − pF

C_oss(eff.) Effective Output Capacitance V_DS= 0 to 400 V, V_GS= 0 V − 553 − pF

C_oss(er.) Energy Related Output Capacitance V_DS= 0 to 400 V, V_GS= 0 V − 83 − pF

Q_g(total) Total Gate Charge at 10 V V_DS= 400 V, I_D= 15 A,

V_GS = 10 V (Note 4) − 58 − nC

Q_gs Gate−to−Source Gate Charge − 19 − nC

Q_gd Gate−to−Drain “Miller” Charge − 23 − nC

ESR Equivalent Series Resistance F = 1 MHz − 2 − W

SWITCHING CHARACTERISTICS, V_GS = 10 V

t_d(on) Turn-On Delay Time V_DD= 400 V, I_D= 15 A,

V_GS= 10 V, R_G= 4.7W (Note 4)

− 31 − ns

t_r Rise Time − 23 − ns

t_d(off) Turn-Off Delay Time − 67 − ns

t_f Fall Time − 4.6 − ns

SOURCE−DRAIN DIODE CHARACTERISTICS

I_S Maximum Continuous Source−to−Drain Diode Forward Current − − 30 A

ISM Maximum Pulsed Source−to−Drain Diode Forward Current − − 69 A

VSD Source−to−Drain Diode Forward Voltage VGS= 0 V, ISD= 15 A − − 1.3 V t_rr Reverse−Recovery Time V_GS= 0 V, I_SD= 15 A,

dIF/dt = 100 A/ms − 92 − ns

Q_rr Reverse−Recovery Charge − 322 − nC

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

4. Essentially independent of operating temperature typical characteristics.

TYPICAL CHARACTERISTICS

Figure 1. On−Region Characteristics V_DS, DRAIN−SOURCE VOLTAGE (V)

20 10 1

10.1 10 100

Figure 2. Transfer Characteristics

Figure 3. On−Resistance Variation vs. Drain Current and Gate Voltage

V_GS, GATE−TO−SOURCE VOLTAGE (V)

I_D, DRAIN CURRENT (A)

8 7

6 5

4 3

12 10 100

60

50 70

40 30 20 10 00

0.1 0.2 0.3

Figure 4. Body Diode Forward Voltage Variation vs. Source Current and Temperature

V_SD, BODY DIODE FORWARD VOLTAGE (V) 2.0 1.5

1.0 0.5

0.0010 0.01 0.1 1 10

10 100 1K 10K 100K

ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A)IS, REVERSE DRAIN CURRENT (A)

ACITANCE (pF)

T_J = 150°C T_J = 25°C

TJ = −55°C V_DS = 20 V

250 ms Pulse Test

T_J = 150°C

T_J = 25°C

T_J = −55°C V_GS = 0 V

250 ms Pulse Test

T_C = 25°C VGS = 10 V

5.5 V 6.0 V 6.5 V 7.0 V 8.0 V

V_GS = 10 V

V_GS = 20 V

C_iss

C_oss VGS = 0 V

f = 1 MHz RDS(on), DRAIN−SOURCE ON−RESISTANCE (mW)

4 6 7 8 10

−SOURCE VOLTAGE (V)

5

9 V_DS = 130 V

VDS = 400 V ID = 15 A

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TYPICAL CHARACTERISTICS

Figure 7. Breakdown Voltage Variation vs.

Temperature

T_J, JUNCTION TEMPERATURE (°C)

175 125

75 25

−25 0.8−75

0.9 1.0 1.1 1.2

Figure 8. On−Resistance Variation vs.

Temperature

Figure 9. Maximum Safe Operating Area

T_J, JUNCTION TEMPERATURE (°C)

V_DS, DRAIN−SOURCE VOLTAGE (V)

175 125

75 25

−25 0−75

0.5 1.0 1.5 2.0 2.5 3.0

1000 100

10 0.11

1 10 100

Figure 10. Maximum Drain Current vs. Case Temperature

Figure 11. E_OSS vs. Drain−to−Source Voltage

T_C, CASE TEMPERATURE (°C)

VDS, DRAIN−TO−SOURCE VOLTAGE (V)

150 125

100 75

50 025

10 20 30 40

600 500 400 300 200 100 00

2.5 5.0 7.5 10.0 12.5 15.0

BVDSS, DRAIN−TO−SOURCE BREAKDOWN VOLTAGE (Normalized) RDS(on), DRAIN−SOURCE ON−RESISTANCE (Normalized)

ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A)

EOSS (mJ)

TC = 25°C R_qJC = 0.52°C/W Single Pulse

RDS(on) Limit

100 ms

1 ms

10 ms

100 ms/DC

ID = 15 A V_GS = 10 V V_GS = 0 V

I_D = 10 mA

TYPICAL CHARACTERISTICS

Figure 12. Transient Thermal Response t, RECTANGULAR PULSE DURATION (sec)

0.1 0.01

0.001 0.0001

0.00001 0.001

0.01 0.1 10

r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (Normalized)

1 Single Pulse

Duty Cycle = 0.5 0.2

0.1 0.05 0.02 0.01

P_DM

t₁

Notes:

Z_qJC (t) = r(t) x R_qJC R_qJC = 0.52°C/W

Peak TJ = PDM x Z_qJC (t) + TC

Duty Cycle, D = t1/t2 t₂

1

DEVICE ORDERING INFORMATION

Device Package Shipping^†

NVBG110N65S3F D2PAK−7L 800 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

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Figure 13. Gate Charge Test Circuit & Waveform

Figure 14. Resistive Switching Test Circuit & Waveforms

Figure 15. Unclamped Inductive Switching Test Circuit & Waveforms RL

V_DS VGS

VGS

RG

DUT

VDD

V_DS

V_GS10%

90%

10%

90% 90%

t_on t_off

t_r t_f

td(on) td(off)

Q_g

Q_gd Q_gs

VGS

Charge V_DS

V_GS

R_L

DUT IG = Const.

V_DD VDS

R_G

VGS DUT

L

ID

tp

V_DD

t_p Time

IAS

BV_DSS

I_D(t)

V_DS(t) E_AS+1

2@LI_AS²

DUT

L

VDD

RG

I_SD

V_DS +

−

VGS

Same Type as DUT

− dv/dt controlled by R_G

− I_SD controlled by pulse period Driver

V_GS (Driver)

ISD

(DUT)

V_DS

(DUT) V_SD

I_RM

10 V

di/dt

V_DD I_FM, Body Diode Forward Current

Body Diode Reverse Current

Body Diode Recovery dv/dt

Body Diode Forward Voltage Drop D+ Gate Pulse Width

Gate Pulse Period

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PACKAGE DIMENSIONS

D²PAK7 (TO−263−7L HV) CASE 418BJ

ISSUE B

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