MOSFET – N-Channel, SUPERFET) II 600 V, 47 A, 70 m

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SUPERFET ⁾ II

600 V, 47 A, 70 mW

FCH47N60

Description

SuperFET II MOSFET is ON Semiconductor’s first generation of high voltage super−junction (SJ) MOSFET family that is utilizing charge balance technology for outstanding low onresistance and lower gate charge performance. This technology is tailored to minimize conduction loss, provide superior switching performance, dv/dt rate and higher avalanche energy. Consequently, SuperFET MOSFET is very suitable for the switching power applications such as PFC, server/telecom power, FPD TV power, ATX power and industrial power applications.

Features

• ^{Typ. R}

DS(on)

= 58 m

• ^{650 V @ T}

J

= 150 ° C

• Ultra Low Gate Charge (Typ. Q

g

= 210 nC)

• Low Effective Output Capacitance (Typ. C

_oss(eff.)

= 420 pF)

• 100% Avalanche Tested

• These Devices are Pb−Free and are RoHS Compliant

Applications

• Telecom / Sever Power Supplies

• Industrial Power Supplies

www.onsemi.com

N-CHANNEL MOSFET

MARKING DIAGRAM

V_DS R_DS(ON) MAX I_D MAX

600 V 70 m @ 10 V 47 A

G

S D

DG S

G

TO−247−3LD CASE 340CK

$Y&Z&3&K FCH 47N60

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ABSOLUTE MAXIMUM RATINGS (T_C = 25°C unless otherwise noted)

Symbol Parameter FCH47N60 Unit

VDSS Drain to Source Voltage 600 V

VGSS Gate to Source Voltage ±30

I_D Drain Current: − Continuous (TC = 25°C) 47 A

− Continuous (TC = 100°C) 29.7

IDM Drain Current: − Pulsed (Note 1) 141 A

EAS Single Pulsed Avalanche Energy (Note 2) 1800 mJ

IAR Avalanche Current (Note 1) 47 A

EAR Repetitive Avalanche Energy (Note 1) 41.7 mJ

dv/dt Peak Diode Recovery dv/dt (Note 3) 4.5 V/ns

PD Power Dissipation (TC = 25°C) 417 W

− Derate Above 25°C 3.33 W/°C

T_J, T_STG Operating and Storage Temperature Range −55 to + 150 °C

T_L Maximum Lead Temperature for Soldering, 1/8″ from Case for 5 seconds 300 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

1. Repetitive rating: pulse−width limited by maximum junction temperature.

2. I_AS = 18 A, V_DD = 50 V, R_G = 25 , Starting TJ = 25 °C.

3. I_SD≤ 48 A, di/dt ≤ 200 A/s, V_DD≤BV_DSS, Starting T_J = 25 °C.

PACKAGE MARKING AND ORDERING INFORMATION

Part Number Top Marking Package Packing Method Reel Size Tape Width Quantity

FCH47N60_F133 FCH47N60 TO−247 Tube N/A N/A 30 Units

THERMAL CHARACTERISTICS

Symbol Parameter FCH47N60 Unit

R_JC Thermal Resistance, Junction to Case, Max. 0.3 °C/W

R_JA Thermal Resistance, Case−to−Sink, Typ. 0.24 °C/W

R_JA Thermal Resistance, Junction to Ambient, Max. 41.7 °C/W

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ELECTRICAL CHARACTERISTICS (T_C = 25°C unless otherwise noted)

Symbol Parameter Test Condition Min. Typ. Max. Unit

OFF CHARACTERISTICS

BV_DSS Drain to Source Breakdown Voltage VGS = 0 V, ID = 250 A, TC = 25°C 600 − − V VGS = 0 V,ID = 250 A, TC = 150°C − 650 −

BVDSS

/TJ

Breakdown Voltage Temperature

Coefficient I_D = 250 A, Referenced to 25°C − 0.6 − V/°C

BV_DS Drain to Source Avalanche Breadown

Voltage V_GS = 0 V, I_D = 47 A − 700 − V

I_DSS Zero Gate Voltage Drain Current V_DS = 600 V, V_GS = 0 V − − 1 A

V_DS = 480 V, T_C = 125 °C − − 10

IGSS Gate to Body Leakage Current VGS = ±30 V, VDS = 0 V − − ±100 nA

ON CHARACTERISTICS

VGS(th) Gate Threshold Voltage V_GS = V_DS, I_D = 250 A 3 − 5 V

RDS(on) Static Drain to Source On Resistance VGS = 10 V, ID = 23.5 A − 0.058 0.070

gFS Forward Transconductance VDS = 40 V, ID = 23.5 A − 40 − S

DYNAMIC CHARACTERISTICS

C_iss Input Capacitance V_DS = 25 V, V_GS = 0 V, f = 1.0 MHz − 5900 8000 pF

Coss Output Capacitance − 3200 4200 pF

Crss Reverse Transfer Capacitance − 250 − pF

C_oss Output Capacitance V_DS = 480 V, V_GS = 0 V, f = 1.0 MHz − 160 − pF

C_oss(eff.) Effective Output Capacitance V_DS = 0 V to 400 V, V_GS = 0 V − 420 − pF SWITCHING CHARACTERISTICS

td(on) Turn-On Delay Time VDD = 300 V, ID = 47 A, V_GS = 10 V, R_g = 25 (Note 4)

− 185 430 ns

t_r Turn−On Rise Time − 210 450 ns

t_d(off) Turn-Off Delay Time − 520 1100 ns

t_f Turn−Off Fall Time − 75 160 ns

Q_g(tot) Total Gate Charge at 10 V VDS = 480 V, ID = 47 A, VGS = 10 V

(Note 4) − 210 270 nC

Q_gs Gate to Source Gate Charge − 38 − nC

Q_gd Gate to Drain “Miller” Charge − 110 − nC

DRAIN-SOURCE DIODE CHARACTERISTICS

I_S Maximum Continuous Source to Drain Diode Forward Current − − 47 A

I_SM Maximum Pulsed Drain to Source Diode Forward Current − − 141 A

V_SD Drain to Source Diode Forward Voltage V_GS = 0 V, I_SD = 47 A − − 1.4 V

t_rr Reverse Recovery Time V_GS = 0 V, I_SD = 47 A,

dI_F/dt = 100 A/s − 590 − ns

Q_rr Reverse Recovery Charge − 25 − C

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

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TYPICAL CHARACTERISTICS

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics

Figure 3. On−Resistance Variation vs. Drain

Current and Gate Voltage Figure 4. Body Diode Forward Voltage Variation vs. Source Current and Temperature

V_GS

Top: 15.0 V 10.0 V 8.0 V 7.0 V 6.5 V 6.0 V Bottom: 5.5 V

*Notes:

1. 250 s Pulse Test 2. T_C = 25°C

10⁻¹ 10⁰ 10¹

10⁰ 10¹ 10²

2 4 6 8 10

10⁰ 10¹ 10²

150°C

−55°C 25°C

*Notes:

1. V_DS = 40 V 2. 250 s Pulse Test V_GS, Gate−Source Voltage [V]

ID, Drain Current [A]

0.00 0.05 0.10 0.15 0.20

0 20 40 60 80 100 120 140 160 180 200 V_GS = 10 V

V_GS = 20 V

*Note: T_J = 25°C I_D, Drain Current [A]

RDS(ON) [], Drain−Source On−Resistance

25°C 150°C

*Notes:

1. V_GS = 0 V 2. 250 s Pulse Test

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

10⁰ 10¹ 10²

V_SD, Source−Drain Voltage {V]

IDR, Reverse Drain Current [A]

5000 10000 15000 20000 25000 30000

Ciss = Cgs + Cgd (Cds = shorted Coss = Cds + Cgd

Crss = Cgd

*Notes:

1. VGS = 0 V 2. f = 1 MHz Coss

Ciss

C_rss

Capacitance [pF]

2 4 6 8 10 12

*Note: I_D = 47 A V_DS = 400 V

V_DS = 250 V V_DS = 100 V

VGS, Gate−Source Voltage [V]

V_DS, Drain−Source Voltage [V]

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TYPICAL CHARACTERISTICS

Figure 7. Breakdown Voltage Variation vs. Temperature

Figure 8. On−Resistance Variation vs.

Temperature

Figure 9. Safe Operating Area Figure 10. Maximum Drain Current vs.

Case Temperature 0.8

0.9 1.0 1.1 1.2

−100 −50 0 50 100 150 200

*Notes:

1. V_GS = 0 V 2. I_D = 250 A

T_J, Junction Temperature [°C]

BVDSS, (Normalized) Drain−Source Breakdown Voltage

0.0 0.5 1.0 1.5 2.0 2.5 3.0

−100 −50 0 50 100 150 200

T_J, Junction Temperature [°C]

*Notes:

1. V_GS = 10 V 2. I_D = 47 A RDS(ON), (Normalized) Drain−Source On−Resistance

DC 10 ms 1 ms

*Notes:

1. T_C = 25°C 2. T_J = 150°C 3. Single Pulse Operation in This Area is Limited by R_DS(on)

100 s

10⁰ 10¹ 10² 10³

10⁰ 10¹ 10²

10⁻¹

10⁻²

V_DS, Drain−Source Voltage [V]

25 50 75 100 125 150

0 10 20 30 40 50

T_C, Case Temperature [°C]

single pulse 0.02

0.2

0.05 0.1

0.01

t1

PDM

t2

*Notes:

1. Z_JC(t) = 0.3°C/W Max.

2. Duty Factor, D = t₁/t₂ 3. T_JM − T_C = P_DM * Z_JC(t) D = 0.5

10⁻² 10⁻¹

JC(t), Thermal Response [°C/W]

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Figure 12. Gate Charge Test Circuit & Waveform Q_g Q_gd Q_gs

VGS

Charge VDS

V_GS

R_L

DUT IG = Const.

Figure 13. Resistive Switching Test Circuit & Waveforms

Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms R_L

VDS

V_GS

R_G

DUT

V_DD

VDS

V_GS10%

90%

10%

90% 90%

ton toff

tr tf

td(on) td(off)

V_DD V_DS

R_G V_GS DUT

L

I_D

t_p

V_DD

tp Time

I_AS BV_DSS

I_D(t)

V_DS(t) E_AS+1

2@LI_AS²

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DUT

L

V_DD R_G

I_SD

V_SD +

−

V_GS

Same Type as DUT

− dv/dt controlled by R_G

− I_SD controlled by pulse period Driver

V_GS (Driver)

I_SD (DUT)

V_DS

(DUT) V_SD

IRM

10 V

di/dt

VDD

IFM, Body Diode Forward Current

Body Diode Reverse Current Body Diode Recovery dv/dt

Body Diode Forward Voltage Drop D+Gate Pulse Width

Gate Pulse Period

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TO−247−3LD SHORT LEAD CASE 340CK

ISSUE A

DATE 31 JAN 2019

XXXX = Specific Device Code A = Assembly Location Y = Year

WW = Work Week ZZ = Assembly Lot Code

*This information is generic. Please refer to device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may GENERIC

MARKING DIAGRAM*

AYWWZZ XXXXXXX XXXXXXX

E

D

L1 E2

(3X) b (2X) b2

b4

(2X) e

Q

L

0.25 ^M B A ^M A

A1 A2 A

c

B

D1 P1

S P

E1

D2

1 2 3 2

DIM MILLIMETERS MIN NOM MAX A 4.58 4.70 4.82 A1 2.20 2.40 2.60 A2 1.40 1.50 1.60 b 1.17 1.26 1.35 b2 1.53 1.65 1.77 b4 2.42 2.54 2.66 c 0.51 0.61 0.71 D 20.32 20.57 20.82

D1 13.08 ~ ~

D2 0.51 0.93 1.35 E 15.37 15.62 15.87

E1 12.81 ~ ~

E2 4.96 5.08 5.20

e ~ 5.56 ~

L 15.75 16.00 16.25 L1 3.69 3.81 3.93

P 3.51 3.58 3.65

P1 6.60 6.80 7.00

Q 5.34 5.46 5.58

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MOSFET – N-Channel, SUPERFET) II 600 V, 47 A, 70 m

SUPERFET ) II

600 V, 47 A, 70 mW

FCH47N60

• Typ. R

= 58 m

• 650 V @ T

= 150 ° C

• Ultra Low Gate Charge (Typ. Q

= 210 nC)

• Low Effective Output Capacitance (Typ. C

= 420 pF)

• 100% Avalanche Tested

• These Devices are Pb−Free and are RoHS Compliant

• Telecom / Sever Power Supplies

• Industrial Power Supplies

TYPICAL CHARACTERISTICS

TYPICAL CHARACTERISTICS

DIM MILLIMETERS MIN NOM MAX A 4.58 4.70 4.82 A1 2.20 2.40 2.60 A2 1.40 1.50 1.60 b 1.17 1.26 1.35 b2 1.53 1.65 1.77 b4 2.42 2.54 2.66 c 0.51 0.61 0.71 D 20.32 20.57 20.82

D1 13.08 ~ ~

D2 0.51 0.93 1.35 E 15.37 15.62 15.87

E1 12.81 ~ ~

E2 4.96 5.08 5.20

e ~ 5.56 ~

L 15.75 16.00 16.25 L1 3.69 3.81 3.93

P 3.51 3.58 3.65

P1 6.60 6.80 7.00

Q 5.34 5.46 5.58

SUPERFET ⁾ II

• ^{Typ. R}

• ^{650 V @ T}