第 1 章 序論
1.7 参考文献
[1] (2017). IRDS Report. [Online]. Available: http://irds.ieee.org/reports (アクセス 日: 2019/2/26)
[2] International Technology Roadmap for Semiconductors (ITRS) [Online].
Available: http://www.itrs2.net/itrs-reports.html (アクセス日: 2019/2/26) [3] K. Takeuchi, and T. Mogami, “A new multiple transistor parameter design
methodology for high speed low power SoC's,” IEDM tech. dig., Dec. 2001, pp.
515–518.
[4] 内田 建, 杉井信之, 竹内 潔, 集積ナノデバイス, 平本俊郎 (編), 丸善 出版株式会社, 東京, 2009, pp. 141–147.
[5] R. H. Dennard, F. H. Gaensslen, V. L. Rideout, E. Bassous, and A. R. LeBlanc,
“Design of ion-implanted MOSFET's with very small physical dimensions,”
IEEE Journal of Solid-State Circuits, vol. SC-9, no. 5, pp. 256–268, Oct. 1974.
[6] T. Kanemura et al., “Improvement of Drive Current in Bulk-FinFET using Full 3D Process/Device Simulations,” 2006 International Conference on Simulation of Semiconductor Processes and Devices, Monterey, CA, 2006, pp. 131–134.
[7] T. Chiarella, L. Witters, A. Mercha, C. Kerner, M. Rakowski, C. Ortolland, L.-Å. Ragnarsson, B. Parvais, A. De Keersgieter, S. Kubicek, A. Redolfi, C.
Vrancken, S. Brus, A. Lauwers, P. Absil, S. Biesemans, and T. Hoffmann,
“Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession,” Solid-State Electronics, vol. 54, no. 9, pp. 855–860, May 2010.
[8] T. Takahashi, N. Beppu, K. Chen, S. Oda, and K. Uchida, “Self-heating effects and analog performance optimization of fin-type field-effect transistors,”
Japanese Journal of Applied Physics, vol. 52, no. 4S, pp. 04CC03-1–04CC03-6, Feb. 2013.
[9] A. R. Brown, N. Daval, K. K. Bourdelle, B. Nguyen and A. Asenov,
“Comparative Simulation Analysis of Process-Induced Variability in Nanoscale SOI and Bulk Trigate FinFETs,” IEEE Transactions on Electron Devices, vol.
60, no. 11, pp. 3611–3617, Nov. 2013.
[10] T. B. Hook et al., “SOI FinFET versus bulk FinFET for 10nm and below,” 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Millbrae, CA, 2014, pp. 1–3.
[11] Y. Morita, T. Mori, S. Migita, W. Mizubayashi, A. Tanabe, K. Fukuda, T.
Matsukawa, K. Endo, S. O’uchi, Y. X. Liu, M. Masahara, and H. Ota,
“Performance enhancement of tunnel field-effect transistors by synthetic Electric field effect,” IEEE Electron Device Lett., vol. 35, no. 7, pp. 792–794, Jul. 2014.
28
[12] A. M. Ionescu, and H. Riel, “Tunnel field-effect transistors as energy-efficient electronic switches,” Nature, vol. 479, pp. 329–337, Nov. 2011.
[13] K. Tomioka, M. Yoshimura, and T. Fukui, “Steep-slope tunnel field-effect transistors using III–V nanowire/Si heterojunction,” in VLSI Tech. Dig., Jun.
2012. pp. 47–48.
[14] H. Lu, and A. Seabaugh, “Tunnel field-effect transistors: State-of the-art,” IEEE J. Electron Devices Soc., vol. 2, no. 4, pp. 44–49, Jul. 2014.
[15] T. Mori, W. Mizubayashi, Y. Morita, S. Migita, K. Fukuda, N. Miyata, T. Yasuda, M. Masahara, and H. Ota, “Effect of hot implantation on ON-current enhancement utilizing isoelectronic trap in Si-based tunnel field-effect transistors,” Appl. Phys. Express, vol. 8, no. 3, pp. 036503-1–036503-3, Feb.
2015.
[16] S. Salahuddin, and S Datta, “Use of negative capacitance to provide voltage amplification for low power nanoscale devices,” Nano Lett., vol. 8, no. 2, pp.
405–410, Dec. 2007.
[17] K. S. Li, P.-G. Chen, T.-Y. Lai, C. H. Lin, C.-C. Cheng, C.-C. Chen, Y.-J. Wei, Y.-F. Hou, M.-H. Liao, M.-H. Lee, J.-M. Sheih, W.-K. Yeh, F.-L. Yang, S.
Salahuddin, and C. Hu, “Sub-60mV-swing negative-capacitance FinFET without hysteresis,” in IEDM Tech. Dig., Dec. 2015, pp. 620–623.
[18] C.-C. Fan, C.-H. Cheng, Y.-R. Chen, C. Liu, and C.-Y. Chang, “Energy-efficient HfAlOx NCFET: Using gate strain and defect passivation to realize nearly hysteresis-free sub-25mV/dec switch with ultralow leakage,” in IEDM Tech.
Dig., Dec. 2017, pp. 561–564.
[19] B. Obradovic, T. Rakshit, R. Hatcher, J. A. kittl, and M. S. Rodder, “Ferroelectric Switching Delay as Cause of Negative Capacitance and the Implications to NCFETs,” in Symp. on LVSI Tech. Dig., Jun. 2018, pp. 51–52.
[20] Q. Huang, R. Huang, Y. Pan, S. Tan, and Y. Wang, “Resistive-gate field-effect transistor: A novel steep-slope device based on a metal-insulator-metal-oxide gate stack,” IEEE Electron Device Lett., vol. 35, no. 8, pp. 877–879, Aug. 2014.
[21] R. Nathanael, V. Pott, H. Kam, J. Jeon, and T.-J. K. Liu, “4-terminal relay technology for complementary logic,” in IEDM Tech. Dig., Dec. 2009, pp. 1–4.
[22] T.-J. K. Liu, J. Jeon, R. Nathanael, H. Kam, V. Pott, and E. Alon, “Prospects for MEM logic switch technology,” in IEDM Tech. Dig., Dec. 2010, pp. 424–427.
[23] K. Gopalakrishnan, P. B. Griffin, and J. D. Plummer, “IMOS: A novel semiconductor fevice with a subthreshold slope lower than kT/q,” in IEDM tech.
Dig., Dec. 2002, pp. 289–292.
29
[24] E. Toh, G. H. Wang, L. Chan, G. Samudra and Y. Yeo, "A double-spacer I-MOS transistor with shallow source junction and lightly doped drain for reduced operating voltage and enhanced device performance," IEEE Electron Device Letters, vol. 29, no. 2, pp. 189–191, Feb. 2008.
[25] A. Savio, S. Monfray, C. Charbuillet, and T. Skotnicki, “On the limitations of silicon for I-MOS integration,” IEEE Trans. Electron Devices, vol. 56, no. 5, pp.
1110–1117, May 2009.
[26] K. Gopalakrishnan, R. Woo, C. Jungemann, P. B. Griffin, and J. D. Plummer,
“Impact ionization MOS (I-MOS)—Part II: Experimental results,” IEEE Trans.
Electron Devices, vol. 52, no. 1, pp. 77–84, Jan. 2005.
[27] 吉見 信, SOIデバイス技術 –実践的基礎と応用-, EDリサーチ社, 東京,
2005, pp. 24–31.
[28] J. R. Davis, A. E. Glaccum, K. Reeson, and P. L. F. Hemment, “Improved Subthreshold Characteristics of n-Channel SOI Transistors,” IEEE Electron Device Lett., vol. EDL-7, no. 10, pp. 570–572, Oct. 1986.
[29] J. G. Fossum, R. Sundaresan, and M. Matloubian, “Anomalous Subthreshold Current-Voltage Characteristics of n-Channel SOI MOSFET’s,” IEEE Electron Device Lett., vol. EDL-8, no. 11, pp. 544–546, Nov. 1987.
[30] B.-Y. Mao, R. Sundaresan, C.-E. D. Chen, M. Matloubian, and G. Pollack, “The Characteristics of CMOS Devices in Oxygen-Implanted Silicon-on-Insulator Structures,” IEEE Trans. Electron Devices, vol. 35, no. 5, pp. 629–633, May 1988.
[31] C.-E. D. Chen, M. Matloubian, R. Sundaresan, B.-Y. Mao, C. C. Wei, and G. P.
Pollack, “Single-Transistor Latch in SOI MOSFET’s,” IEEE Electron Device Lett., vol. 9, no. 12, pp. 636–638, Dec. 1988.
[32] J. R. Davis, G. A. Armstrong, N.J. Thomas, and A. Doyle, “Thin-film SOI CMOS transistors with p+-Poly silicon gates,” IEEE Trans. Electron Devices, vol. 38, no. 1, pp. 32–38, Jan. 1991.
[33] J.-Y. Choi, and J. G. Fossum, “Analysis and control of floating-body bipolar effect in fully depleted submicrometer SOI MOSFET’s,” IEEE Trans. Electron Devices, vol. 38, no. 6, pp. 1384–1391, Jun. 1991.
[34] J. Gautier, and A.-J. A.-Herve, “A Latch Phenomenon in Buried N-Body SOI NMOSFET’s,” IEEE Electron Device Lett., vol. 12, no. 7, pp. 372–374, Jul. 1991.
[35] J. S. T. Huang, J.S. Kueng, and T. Fabian, “An Analytical Model for Snapback in n-Channel SOI MOSFET's,” IEEE Trans. Electron Devices, vol. 38, no. 9, pp.
2082–2091, Sep. 1991.
30
[36] T.-D. Her, P. S. Liu, D. S. Quon, G. P. Li, R. Kjar, and J. White, “Parasitic bipolar transistor induced latch and degradation in SOI MOSFET’s,” in IEEE Int. SOI Conf., pp. 124–125, Oct. 1991.
[37] M. A. Pavanello, J. A. Martino, and D. Flandre, “Graded-channel fully depleted Silicon-On-Insulator nMOSFET for reducing the parasitic bipolar effects,”
Solid-State Electron., vol. 44, no. 6, pp. 917–922, Jun. 2000.
[38] M. Jurczak, “Memories on SOI: Floating Body Cell Memory,” Training Course EUROSOI, Granada, Jan. 2011.
[39] Z. Lu, N. Collaert, M. Aoulaiche, B. De Wachter, A. De Keersgieter, J. G.
Fossum, L. Altimime, and M. Jurczak, “Realizing super-steep subthreshold slope with conventional FDSOI CMOS at low-bias voltages,” in IEDM Tech. Dig. Dec.
2010, pp. 16.6.1–16.6.3.
[40] J. G. Fossum, and Z. Lu, “Anomalous floating-body effects in SOI MOSFETs:
low-voltage CMOS?,” in IEEE Int. SOI Conf., Oct. 2011, pp. 1–2.
[41] K. Nishiguchi, and A. Fujiwara, “Nanowire metal-oxide-semiconductor field-effect transistors with small subthreshold swing driven by body-bias field-effect,”
Appl. Phys. Express, vol. 5, no. 8, pp. 080052-1–080052-3, Aug. 2012.
[42] S. Cristoloveanu, J. Wan and A. Zaslavsky, "A Review of Sharp-Switching Devices for Ultra-Low Power Applications," in IEEE Journal of the Electron Devices Society, vol. 4, no. 5, pp. 215-226, Sep. 2016.
[43] A. Padilla, C. W. Yeung, C. Shin, C. Hu, and T.-J. K. Liu, “Feedback FET: A novel transistor exhibiting steep switching behavior at low bias voltages,” in IEDM Tech. Dig., Dec. 2008, pp. 171–174.
[44] C. W. Yeung, A. Padilla, T.-J. K. Liu, and C. Hu, “Programming characteristics of the steep turn-on/off feedback FET (FBFET),” in Symp. on LVSI Tech. Dig., Jun. 2009, pp. 176–177.
[45] J. Wan, S. Cristoloveanu, C. L. Royer, and A. Zaslavsky, “A feedback silicon-on-insulator steep switching device with gate-controlled carrier injection,” Solid State Electron., vol. 76, pp. 109–111, Oct. 2012.
[46] J. Wan, C. L. Royer, A. Zaslavsky, and S. Cristoloveanu, “Progress in Z2-FET 1T-DRAM: Retention time, writing modes, selective array operation, and dual bit storage,” Solid State Electron., vol. 84, pp. 147–154, Jun. 2013.
[47] J. Wan, C. L. Royer, A. Zaslavsky, and S. Cristoloveanu, “A systematic study of the sharp-switching Z2-FET device: From mechanism to modeling and compact memory applications,” Solid State Electron., vol. 90, pp. 2–11, Dec. 2013.
[48] Y. Taur, J. Lacord, M. S. Parihar, J. Wan, S. Martinie, K. Lee, M. Bawedin, J.-C.
31
Barbe, and S. Cristoloveanu, “A comprehensive model on field-effect pnpn devices (Z2-FET),” Solid State Electron., vol. 134, pp. 1–8, Aug. 2017.
[49] C. Navarro et al., “Extended analysis of the Z2-FET: operation as capacitorless eDRAM,” IEEE Trans. Electron Devices, vol. 64, no. 11, pp. 4486–4491, Nov.
2017.
[50] C. Navarro et al., “Z2-FET as capacitor-less eDRAM cell for high-density integration,” IEEE Trans. Electron Devices, vol. 64, no. 12, pp. 4904–4909, Dec.
2017.
[51] S. Navarro et al., “Experimental demonstration of operational Z2-FET memory matrix,” IEEE Electron Device Letters, vol. 39, no. 5, pp. 660–663, May 2018.
[52] S. Cristoloveanu et al., “A review of the Z2-FET 1T-DRAM memory: Operation mechanisms and key parameters,” Solid State Electron., vol. 143, pp. 10–19, May 2018.
[53] M. Duan et al., “Thorough understanding of retention time of Z2FET memory operation,” IEEE Trans. Electron Devices, vol. 66, no. 1, pp. 383–388, Jan. 2019.
[54] A. A. Salman, S. G. Beebe, M. Emam, M. M. Pelella, and D. E. Ioannou, “Field effect diode (FED): A novel device for ESD protection in deep sub-micron SOI technologies,” in IEDM Tech. Dig., Dec. 2006, pp. 1–4.
[55] H. Mulaosmanovic, G. M. Paolucci, C. M. Compagnoni, N. Castellani, G.
Carnevale, P. Fantini, D. Ventrice, A. L. Lacaita, A. S. Spinelli, and A. Benvenuti,
“Working principles of a DRAM cell based on gated-thyristor bistability,” IEEE Electron Device Lett., vol. 35, no. 9, pp. 921–923, Sep. 2014.
[56] N. Choi, H.-J. Kang, S. Chung, S.-H. Bae, B.-G. Park, and J.-H. Lee, “First demonstration of diode-type 3-D NAND flash memory string having super-steep switching slope,” in VLSI Tech. Dig., Jun. 2017, pp. 204–205.
[57] R. J. M. Vullers, R. van Schaijk, I. Doms, C. Van Hoof, and R. Mertens,
“Micropower energy harvesting,” Solid-State Electron. vol. 53, pp. 684–693, Apr. 2009.
[58] H. T. Friis, “A note on a simple transmission formula,” in Proceedings of the IRE, vol. 34, no. 5, pp. 254-256, May 1946.
[59] J. Kang, P. Y. Chiang, and A. Natarajan, “A 1.2cm2 2.4GHz self-oscillating rectifier antenna achieving –34.5dBm sensitivity for wirelessly powered sensors,”
in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2016, pp. 374–375.
[60] T. Furuta, M. Ito, N. Nambo, K. Itoh, K. Noguchi, and J. Ida “The 500MHz band low power rectenna for DTV in the Tokyo area,” in Proc. IEEE Wireless Power
32
Transfer Conf. (WPTC), May 2016, session 3-2 pp. 1–3.
[61] J. Iwata, J. Ida, T. Furuta, K. Noguchi, and K. Itoh, “Confirmation of high efficiency on rectenna with high impedance antenna and optimized gate controlled diode for RF energy harvesting,” in Proc. of IEEE SENSORS, Nov.
2016, C-16-355 pp. 1–3.
[62] S. M. Sze, and K. K. Ng, Physics of Semiconductor Devices, 3rd ed. New York, NY, USA: Wiley, 2007, pp. 435–436.
[63] E. Donchev, J. S. Pang, P. M. Gammon, A. Centeno, F. Xie, P. K. Petrov, J. D.
Breeze, M. P. Ryan, D. J. Riley, and N. M. N. Alford, “The rectenna device: From theory to practice (a review),” MRS Energy & Sustainability, vol. 1, Jul. 2014.
[64] L. Esaki, “Discovery of the tunnel diode,” IEEE Transactions on Electron Devices, vol. 23, no. 7, pp. 644–647, July 1976.
[65] C. H. P. Lorenz, S. Hemour, W. Li, Y. Xie, J. Gauthier, P. Fay, and K. Wu,
“Breaking the efficiency barrier for ambient microwave power harvesting with heterojunction backward tunnel diodes,” IEEE Trans. Microw. Theory. Tech., vol.
63, no. 12, pp. 4544–4555, Nov. 2015.
[66] T. A. Jokinen, and S. McNamara, “Band-to-Band Tunneling Diode for Ultralow-Voltage Applications,” IEEE Transactions on Electron Devices, vol. 64, no. 6, pp. 2702–2706, Jun. 2017.
[67] H. Liu, X. Li, R. Vaddi, K. Ma, S. Datta, and V. Narayanan, “Tunnel FET RF rectifier design for energy harvesting applications,” IEEE J. Emerg. Sel. Topic Circuits Syst., vol. 4, no. 4, pp. 400–411, Dec. 2014.
[68] J. Núñez, and M. J. Avedillo, “Reducing the impact of reverse currents in tunnel FET rectifiers for energy harvesting applications,” IEEE J. Electron Devices Soc., vol. 5, no. 6, pp. 530–534, Aug. 2017.
33