[PDF] Top 20 J126 e IEICE 2006 4 最近の更新履歴 Hideo Fujiwara J126 e IEICE 2006 4

... Fig. 7 Heuristic of graph division. nection. Our proposed algorithm repeats the division process from a 0-partition, that is, only one block that includes all the memories, to obtain the target partition. As the algo- ... 完全なドキュメントを参照

... A number of approaches have addressed wrapper design [2, 3, 4] which are IEEE 1500 [5] compliant. Similarly, sev- eral test access mechanism (TAM) architectures have been proposed [6, 7, 8, 9, 10, 11, 12]. TAM ... 完全なドキュメントを参照

... Email:{hiroyu-i,yoneda,fujiwara}@is.naist.jp Abstract This paper presents a non-scan design-for-testability (DFT) method that guarantees complete fault efficiency (FE) for register transfer level (RTL) circuits. We ... 完全なドキュメントを参照

... 4 Diagnosis algorithm The diagnosis procedure is based on a search function that considers an erroneous output block called signa- ture and returns an erroneous input block that produces the given signature. Such ... 完全なドキュメントを参照

... 2. Observing Responses by a Slow Speed Tester Before providing a formulation of the problem we de- scribe the method given in [19] that can identify all failing responses by observing scan outputs even if the CUT test ... 完全なドキュメントを参照

... decreased, increases dramatically from 8.69% at P max = infinity to 18.36% at P max = 1500. This can be attributed to the fact that wider W ext and lower P max makes splitting the domains more effective because of the ... 完全なドキュメントを参照

... E-mail: † t7hosoka@cit.nihon-u.ac.jp, ††c67010@cit.nihon-u.ac.jp,‡fujiwara@is.naist.jp Abstract Scan testing is one of the most popular test methods for VLSIs. However, since scan testing is not based on the ... 完全なドキュメントを参照

... 4.2 Overview The aim of this algorithm is to find the minimum number of levels of cliques. Since the problem is NP- hard, we use a heuristic algorithm shown in Fig. 7. We first construct the compatibility graph G ... 完全なドキュメントを参照

... 4. Test Generation Procedure In this section, we discuss the test generation procedure for gate-level circuits where one vertex represents a flip-flop instead of a register. The discussion for the RTL circuits can ... 完全なドキュメントを参照

... nine books on these topics (including two in press), published over 320 papers in journals and refereed conference proceedings, and given over 130 invited, keynote, and plenary talks. Prof. Chakrabarty is a Fellow of ... 完全なドキュメントを参照

... If N > P(P−1), Eq. (10) is always larger than Eq. (9). There- fore, j = 0 is the solution that minimizes Eq. (8).
A typical tester can operate at about 50 MHz and the CUT test frequency in modern DSM circuits ... 完全なドキュメントを参照

... Proposed 50 477,836 99.999 100.000 1 0 6.98 25 468,620 99.999 99.999 0 4 8.19 aborted faults, and test generation time, respectively. The combinational part for the proposed methods in- clude the confusion ... 完全なドキュメントを参照

... at time t + k behaves in accordance with the following equa- tion. z (t + k) = x(t) ⊕ f (x(t + 1), x(t + 2), . . . , x(t + k)). Here, we introduce another class of generalized shift reg- isters called generalized ... 完全なドキュメントを参照

... 近 の 並 列 計 算に お い て 重 要と され て い る 通 信コ スト を ，同 期 周 期 L，通信路帯域幅の 逆数 g，パケット サ イズ B といったパラ メータに より 表すことを 可能にし たモデ ル であ る．本論文では ，デ ータ数 n の選 択 問題に 対し ， p 個のプ ロセッサを 用いて BSP モデル上で任意の整数 d (1 < ... 完全なドキュメントを参照

... 5.1 DFT Element Additional hardware elements of DFT are multiplexer (MUX), hold function and thru function. We use a MUX to make a new RTL path from a PI to a register. A hold function is added to a register for the ... 完全なドキュメントを参照

... 性質を満たすので，提案手法の面積オーバヘッドが 0 となった． 完全スキャン設計法，強可検査法及び提案手法は完 全故障検出効率を達成し，テスト容易化設計前の回路 と比較して大幅にテスト生成時間を削減できた．また， 完全スキャン設計法，強可検査法及び提案手法は，同 程度のテスト生成時間となった．一方，提案手法と強 可検査法は，スキャンシフト操作を必要としないので ... 完全なドキュメントを参照

... In this table, compared with the conventional full scan test, when N = 2, N = 3 and N = 4, the average power is re- duced up to 61.8%, 72.7% and 75.6% respectively. The peak power dissipation is also reduced ... 完全なドキュメントを参照

... # Experiments are carried out for the following five cases: (1) Not shared (All the memories have individual BIST wrapper.), (2) Parallel connection (Memory BIST logic is shared by using only the parallel connection as ... 完全なドキュメントを参照

... Faculty Fellow, Research Institute of Economy, Trade & Industry (RIETI), July 2013–March 2016. Associate member, The Science Council of Japan (SCJ), March 2006–September 2008. CESifo Research Network Fellow, ... 完全なドキュメントを参照

...  今後はHack For Iwate、Hack For Miyagi、Hack For Fukushimaといったように各ディビジョンで現 地に即した活動を進めていき、東京からはそれをサ ポートしていく、という形になりつつあります。構 想としては、復興支援だけでなく、次に何か起きた ときのための備えとしての防災ハッカソンなども やっていくことができればと考えています。 ... 完全なドキュメントを参照