[PDF] Top 20 C194 2008 11 WRTLT 最近の更新履歴 Hideo Fujiwara

... { hiroshi-i, ohtake, fujiwara }@is.naist.jp Abstract Information on false paths in a circuit is useful for de- sign and test. The use of this information may contribute not only in reducing the time required for ... 完全なドキュメントを参照

... Keywords — Test environment, RTL test generation, high-level testing, assignment decision diagrams 1. Introduction The problem of test generation is a basic, essential issue in the area of testing [1][2]. In the ... 完全なドキュメントを参照

... { takashi-y, yoneda, fujiwara }@is.naist.jp Abstract This paper presents a method for designing reconfig- urable wrappers for cores with multiple clock domains to reduce test time. In the proposed method, we divide ... 完全なドキュメントを参照

... The security level of the secure scan architecture is determined by the probability that an attacker can guess right the structure of the. GF 2 SR circuit[r] ... 完全なドキュメントを参照

... The security level of the secure scan architecture is determined by the probability that an attacker can identify the structure of the SR- quasi-equivalent circuit. Hence the attack p[r] ... 完全なドキュメントを参照

... Figure 1 shows an example of an FSM. In this figure, ST0 through ST5 and T0 through T11 show the states and the input values, respectively, of the state transitions (the value of each primary input {0, 1, X}, ... 完全なドキュメントを参照

... The CDkF identification results w.r.t. the generalized model is shown in Table 2(b). As expected, the number of identified false paths is much less compared to the single- transition model. It must be noted that the ... 完全なドキュメントを参照

... Kansai Science City, Nara, Japan fujiwara@is.naist.jp Abstract Similar to test pattern generation, the problem of identifying untestable faults in sequential synchronous circuits remains unsolved. The previously ... 完全なドキュメントを参照

... Fault efficiency 99.32 98.59 96.74 99.91 In the Table, the rows have the following meaning. Row ‘total faults’ shows the number of stuck-at faults in the circuit. Row ‘hard-detected’ gives the number of faults that were ... 完全なドキュメントを参照

... fujiwara@ogu.ac.jp Abstract—Scan design makes digital circuits easily testable, however, it can also be exploited to be used for hacking the chip. We have reported a secure and testable scan design approach by ... 完全なドキュメントを参照

... (a) ADD S1 (b) R-graph of ADD S1 (c)Thru trees (T 1 , T 2 and T 3 ) for ADD S1 Fig. 3 R-graph of thru-testable ADD S1 Example 3. Fig. 3(b) shows the R-graph of the ADD S1. Thru functions t 3 =C is activated by C. ... 完全なドキュメントを参照

... The DFT logic of LRAS shall be tested before testing the circuit-under-test. Since the access mechanism of LRAS is similar to that of SRAM, memory test techniques can be utilized to test LRAS. However, scan flip-flops of ... 完全なドキュメントを参照

... Therefore, a number of approaches have been proposed for the TAM architectures which are not dedicated to test, but reuse the existing components in the SoC. They are roughly classified into three types: 1) the method ... 完全なドキュメントを参照

... The most common Design-for-Testability (DFT) used for SoCs with multiple cores is the design of a test data delivery method, more commonly known as Test Access Mechanism (TAM), and the use of wrappers, which enables ... 完全なドキュメントを参照

... m c i is 2’s exponent and (3) m c i = 1 ...core 11 should be tested at 100 MHz with 64 pins, we observe that there exists no solution for three cases: 1) f AT E = 100 MHz and W max = 32, 2) f AT E = ... 完全なドキュメントを参照

... To guarantee that the proposed method can achieve 100% template level fault e ffi ciency, we show a su ffi cient condition for a processor such that error masking does not occur during t[r] ... 完全なドキュメントを参照

... SR 等価な回路としては，回路の状態正当化・状態 観 測 を 容 易 に 行 う た め に ，接 続 情 報 か ら ス キャン 入 出 力 系 列 を 容 易 に 構 成 で き る こ と が 重 要 で あ る ．そ のためには， I 2 SR ， LF 2 SR ， LFSR ， LF 2 SR+I 2 SR ， LFSR+I 2 SR 等の線形回路構造での SR ... 完全なドキュメントを参照

... SUMMARY Current NoC test scheduling methodologies in the litera- ture are based on a dedicated path approach; a physical path through the NoC routers and interconnects are allocated for [r] ... 完全なドキュメントを参照

... and Hideo FUJIWARA †c) , Fellow SUMMARY The IEEE 1500 standard wrapper requires that its inputs and outputs be interfaced directly to the chip’s primary inputs and out- puts for controllability and observability. ... 完全なドキュメントを参照

... These include frequency and bit-width mismatch be- tween the bus and the cores under test, allocation of bus time slots for an e ffi cient test data delivery schedule that maxi- mizes bu[r] ... 完全なドキュメントを参照