PNP Transistor, Low VCE(sat) 100 V, 2.0 A NSS1C200MZ4, NSV1C200MZ4

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100 V, 2.0 A

NSS1C200MZ4, NSV1C200MZ4

ON Semiconductor’s e

²

PowerEdge family of low V

_CE(sat)

transistors are miniature surface mount devices featuring ultra low saturation voltage (V

_CE(sat)

) and high current gain capability. These are designed for use in low voltage, high speed switching applications where affordable efficient energy control is important.

Typical applications are DC−DC converters and power management in portable and battery powered products such as cellular and cordless phones, PDAs, computers, printers, digital cameras and MP3 players.

Other applications are low voltage motor controls in mass storage products such as disc drives and tape drives. In the automotive industry they can be used in air bag deployment and in the instrument cluster. The high current gain allows e

²

PowerEdge devices to be driven directly from PMU’s control outputs, and the Linear Gain (Beta) makes them ideal components in analog amplifiers.

Features

• NSV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable

• These Devices are Pb−Free, Halogen Free and are RoHS Compliant

MAXIMUM RATINGS (TA = 25°C)

Rating Symbol Max Unit

Collector-Emitter Voltage V_CEO −100 Vdc

Collector-Base Voltage V_CBO −140 Vdc

Emitter-Base Voltage V_EBO −7.0 Vdc

Base Current − Continuous IB 1.0 A

Collector Current − Continuous I_C 2.0 A

Collector Current − Peak ICM 3.0 A

THERMAL CHARACTERISTICS

Characteristic Symbol Max Unit

Total Device Dissipation T_A = 25°C

Derate above 25°C

P_D (Note 1)

800

6.5 mW

mW/°C Thermal Resistance,

Junction−to−Ambient R_qJA (Note 1) 155 °C/W Total Device Dissipation

T_A = 25°C Derate above 25°C

P_D (Note 2)

2.0

15.6 W

mW/°C Thermal Resistance,

Junction−to−Ambient R_qJA (Note 2) 64 °C/W

COLLECTOR 2,4 1

BASE

3 EMITTER www.onsemi.com

−100 VOLTS, 2.0 AMPS PNP LOW V

_CE(sat)

TRANSISTOR

Device Package Shipping^† ORDERING INFORMATION NSS1C200MZ4T1G SOT−223 1000/

SOT−223 CASE 318E

STYLE 1

MARKING DIAGRAM

Top View Pinout C

C E

B 4

1 2 3

1

1C200GAYW

A = Assembly Location

Y = Year

W = Work Week

1C200 = Specific Device Code G = Pb−Free Package

PIN ASSIGNMENT

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OFF CHARACTERISTICS

Collector−Emitter Breakdown Voltage (I_C = −10 mAdc, I_B = 0) V_(BR)CEO −100 Vdc Collector−Base Breakdown Voltage (I_C = −0.1 mAdc, I_E = 0) V_(BR)CBO −140 Vdc Emitter−Base Breakdown Voltage (I_E = −0.1 mAdc, I_C = 0) V_(BR)EBO −7.0 Vdc

Collector Cutoff Current (V_CB = −140 Vdc, I_E = 0) I_CBO −100 nAdc

Emitter Cutoff Current (V_EB = −6.0 Vdc) I_EBO −50 nAdc

ON CHARACTERISTICS DC Current Gain (Note 3)

(I_C = −10 mA, V_CE = −2.0 V) (I_C = −500 mA, V_CE = −2.0 V) (I_C = −1.0 A, V_CE = −2.0 V) (I_C = −2.0 A, V_CE = −2.0 V)

hFE

150 120 80 50

360

Collector−Emitter Saturation Voltage (Note 3) (I_C = −0.1 A, I_B = −0.010 A)

(I_C = −0.5 A, I_B = −0.050 A) (I_C = −1.0 A, I_B = −0.100 A) (I_C = −2.0 A, I_B = −0.200 A)

V_CE(sat)

−0.040

−0.080

−0.125

−0.220

V

Base−Emitter Saturation Voltage (Note 3)

(I_C = −1.0 A, I_B = −0.100 A) VBE(sat)

−0.950 V Base−Emitter Turn−on Voltage (Note 3)

(I_C = −1.0 A, V_CE = −2.0 V) V_BE(on)

−0.850 V Cutoff Frequency

(I_C = −100 mA, V_CE = −5.0 V, f = 100 MHz) f_T

120 MHz

Input Capacitance (V_EB = 3.0 V, f = 1.0 MHz) Cibo 200 pF

Output Capacitance (V_CB = 10 V, f = 1.0 MHz) Cobo 22 pF

3. Pulsed Condition: Pulse Width = 300 msec, Duty Cycle ≤ 2%.

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TYPICAL CHARACTERISTICS

Figure 1. Power Derating T, TEMPERATURE (°C)

150 125

100 75

50 025

0.5 1.0 1.5 2.0 2.5

PD, POWER DISSIPATION (W) T_C

T_A

Figure 2. Thermal Resistance (FR−4 @ 7.6 mm², 1 oz. Cu trace) t, PULSE TIME (sec)

0.01

0.001 1

0.0001 0.1

0.00001 10

0.0000010.1 1 10 100 1000

100 1000

Single Pulse 50% Duty Cycle 20%

10%

5%

2%

1%

R(t) EFFECTIVE TRANSIENT THERMAL RESISTANCE (°C/W)

1 10 100

R(t) EFFECTIVE TRANSIENT THERMAL RESISTANCE (°C/W)

Single Pulse 50% Duty Cycle

20%

10%

5%

2%

1%

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Figure 4. DC Current Gain Figure 5. DC Current Gain I_C, COLLECTOR CURRENT (A)

10 1

0.1 0.01

0.001 0 100 200 300 400

Figure 6. Collector−Emitter Saturation Voltage Figure 7. Collector−Emitter Saturation Voltage I_C, COLLECTOR CURRENT (A)

10 1

0.1 0.01

0.001 0.01

0.1 1

Figure 8. Base−Emitter Saturation Voltage Figure 9. Base−Emitter Saturation Voltage I_C, COLLECTOR CURRENT (A)

10 1

0.1 0.01

0.001 0.2 0.4 0.6 0.8 1.0 1.2 hFE, DC CURRENT GAINVCE(sat), COLLECTOR−EMITTER SATURATION VOLTAGE (V)VBE(sat), BASE−EMITTER SATURA- TION VOLTAGE (V)

V_CE = 2 V 150°C

−55°C 25°C

I_C, COLLECTOR CURRENT (A)

10 1

0.1 0.01

0.001 0 100 200 300 400

hFE, DC CURRENT GAIN

V_CE = 4 V 150°C

−55°C 25°C

IC/IB = 10

150°C

−55°C 25°C

10 1

0.1 0.01

0.001 0.01

0.1 1

VCE(sat), COLLECTOR−EMITTER SATURATION VOLTAGE (V)

IC/IB = 20

150°C

−55°C 25°C

I_C/I_B = 10

150°C

−55°C 25°C

10 1

0.1 0.01

0.001 0.2 0.4 0.6 0.8 1.0 1.2

VBE(sat), BASE−EMITTER SATURA- TION VOLTAGE (V)

I_C/I_B = 50

150°C

−55°C 25°C

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TYPICAL CHARACTERISTICS

Figure 10. Base−Emitter Voltage Figure 11. Collector Saturation Region I_B, BASE CURRENT (A)

1 0.1

0.01 0.001

0.0001 0.01

0.1 1

Figure 12. Input Capacitance Figure 13. Output Capacitance V_BE, EMITTER BASE VOLTAGE (V) V_CB, COLLECTOR BASE VOLTAGE (V)

7 6 5 4 3 2 1 00 100 200 300 400

80 70 60 50 30

20 10 00 20 40 60 80 100 120

0 20 40 60 80 100 120

0.01 0.1 1 10 VCE(sat), COLLECTOR−EMITTER SATURATION VOLTAGE (V)

Cib, INPUT CAPACITANCE (pF) Cob, OUTPUT CAPACITANCE (pF)

fTau, CURRENT−GAIN BANDWIDTH PRODUCT (MHz) IC, COLLECTOR CURRENT (A)

10 1

0.1 0.01

0.001 0.2 0.4 0.6 0.8 1.0 1.2

VBE(on), BASE−EMITTER VOLTAGE (V)

VCE = 2 V

150°C

−55°C 25°C

T_J = 25°C I_C = 0.1 A

0.5 A

1.0 A 2.0 A 3.0 A

8 T_J = 25°C f_test = 1 MHz

40 90 100

T_J = 25°C f_test = 1 MHz

T_J = 25°C f_test = 1 MHz V_CE = 10 V

T_J = 25°C

1 mS 0.5 mS 100 mS

10 mS

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ISSUE R

DATE 02 OCT 2018 SCALE 1:1

q

98ASB42680B DOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 2 SOT−223 (TO−261)

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ISSUE R

DATE 02 OCT 2018

STYLE 4:

PIN 1. SOURCE 2. DRAIN 3. GATE 4. DRAIN

STYLE 6:

PIN 1. RETURN 2. INPUT 3. OUTPUT 4. INPUT

STYLE 8:

CANCELLED STYLE 1:

PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR

STYLE 10:

PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE STYLE 7:

PIN 1. ANODE 1 2. CATHODE 3. ANODE 2 4. CATHODE

STYLE 3:

PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN STYLE 2:

PIN 1. ANODE 2. CATHODE 3. NC 4. CATHODE

STYLE 9:

PIN 1. INPUT 2. GROUND 3. LOGIC 4. GROUND

STYLE 5:

PIN 1. DRAIN 2. GATE 3. SOURCE 4. GATE

STYLE 11:

PIN 1. MT 1 2. MT 2 3. GATE 4. MT 2

STYLE 12:

PIN 1. INPUT 2. OUTPUT 3. NC 4. OUTPUT

STYLE 13:

PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR

1

A = Assembly Location

Y = Year

W = Work Week

XXXXX = Specific Device Code G = Pb−Free Package

GENERIC MARKING DIAGRAM*

AYW XXXXXG

G

(Note: Microdot may be in either location)

*This information is generic. Please refer to device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking.

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or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION