NTLLD4901NF MOSFET – Power, Dual, N-Channel with Integrated Schottky WDFN, (3 mm x 3 mm)

(1)

MOSFET – Power, Dual,

N-Channel with Integrated Schottky WDFN,

(3 mm x 3 mm)

30 V, High Side 11 A / Low Side 13 A

Features

• Co−Packaged Power Stage Solution to Minimize Board Space

• Low Side MOSFET with Integrated Schottky

• Minimized Parasitic Inductances

• Optimized Devices to Reduce Power Losses

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant

Applications

• DC−DC Converters

• System Voltage Rails

• Point of Load

WDFN8 CASE 511BP

MARKING DIAGRAM http://onsemi.com

V_(BR)DSS R_DS(ON) MAX I_D MAX Q1 Top FET

30 V

17.4 mW @ 10 V 25 mW @ 4.5 V 11 A

(8) G2

S2 (5, 6, 7) Q2 Bottom

FET 30 V

13.3 mW @ 10 V 20 mW @ 4.5 V 13 A

(1) G1

S1/D2 (10) D1 (2, 3, 4, 9)

1

4901 = Specific Device Code A = Assembly Location

Y = Year

WW = Work Week G = Pb−Free Package

4901 AYWWG

G 1

(Note: Microdot may be in either location)

See detailed ordering and shipping information in the package

ORDERING INFORMATION 10

9 1 2 3 4

8 7 6 5 PIN CONNECTIONS

D1 S1/D2 G1

D1 D1 D1

G2 S2 S2 S2

(Bottom View)

(2)

MAXIMUM RATINGS (T_J = 25°C unless otherwise stated)

Parameter Symbol Value Unit

Drain−to−Source Voltage Q1 V_DSS 30 V

Drain−to−Source Voltage Q2

Gate−to−Source Voltage Q1 V_GS ±20 V

Gate−to−Source Voltage Q2

Continuous Drain Current R_qJA (Note 1)

Steady State

TA = 25°C Q1 I_D 8.3

TA = 85°C 6.0 A

TA = 25°C Q2 9.6

T_A = 85°C 6.9

Power Dissipation

RqJA (Note 1) TA = 25°C Q1 PD 1.82 W

Q2 1.88

Continuous Drain Current R_qJA ≤ 10 s (Note 1) T_A = 25°C Q1 ID 11

T_A = 85°C 8 A

T_A = 25°C Q2 13

T_A = 85°C 9.1

Power Dissipation

R_qJA ≤ 10 s (Note 1) T_A = 25°C Q1 P_D 3.23 W

Q2 3.27

Continuous Drain Current

R_qJA (Note 2) T_A = 25°C Q1 I_D 5.5

T_A = 85°C 4.0 A

T_A = 25°C Q2 6.3

T_A = 85°C 4.5

Power Dissipation

R_qJA (Note 2) T_A = 25 °C Q1 P_D 0.80 W

Q2 0.81

Pulsed Drain Current TA = 25°C

tp = 10 ms Q1 I_DM 65 A

Q2 70

Operating Junction and Storage Temperature Q1 T_J, T_STG −55 to +150 °C

Q2

Source Current (Body Diode) Q1 I_S 4.2 A

Q2 6.0

Drain to Source DV/DT dV/dt 6 V/ns

Single Pulse Drain−to−Source Avalanche Energy (TJ = 25C, VDD = 50 V,

V_GS = 10 V, I_L = 9.0 A_pk, L = 0.3 mH, R_G = 25 W) Q1 EAS 12 mJ

Single Pulse Drain−to−Source Avalanche Energy (T_J = 25C, V_DD = 50 V,

VGS = 10 V, IL = 9.5 Apk, L = 0.3 mH, RG = 25 W) Q2 EAS 13.5

Lead Temperature for Soldering Purposes

(1/8” from case for 10 s) TL 260 °C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

1. Surface−mounted on FR4 board using 1 sq−in pad, 2 oz Cu

2. Surface−mounted on FR4 board using the minimum recommended pad size of 90 mm²

(3)

THERMAL RESISTANCE MAXIMUM RATINGS

Parameter FET Symbol Value Unit

Junction−to−Ambient – Steady State (Note 3) Q1 R_qJA 68.8

°C/W

Q2 66.4

Junction−to−Ambient – Steady State (Note 4) Q1 R_qJA 156.4

Q2 153.9

Junction−to−Ambient – (t ≤ 10 s) (Note 3) Q1 R_qJA 38.7

Q2 38.2

3. Surface−mounted on FR4 board using 1 sq−in pad, 2 oz Cu

4. Surface−mounted on FR4 board using the minimum recommended pad size of 90 mm² ELECTRICAL CHARACTERISTICS (T_J = 25°C unless otherwise specified)

Parameter FET Symbol Test Condition Min Typ Max Unit

OFF CHARACTERISTICS Drain−to−Source Break-

down Voltage Q1 V_(BR)DSS V_GS = 0 V, I_D = 250 mA 30 V

Q2 30

Drain−to−Source Break- down Voltage Temperature Coefficient

Q1 V_(BR)DSS / TJ

18 mV /

Q2 15 °C

Zero Gate Voltage Drain

Current Q1 I_DSS V_GS = 0 V,

VDS = 24 V T_J = 25°C 1 mA

T_J = 125°C 10

Q2 V_GS = 0 V,

VDS = 24 V T_J = 25°C 500

Gate−to−Source Leakage

Current Q1 I_GSS V_GS = 0 V, VDS = ±20 V ±100 nA

Q2 ±100

ON CHARACTERISTICS (Note 5)

Gate Threshold Voltage Q1 V_GS(TH) V_GS = VDS, I_D = 250 mA 1.2 2.2 V

Q2 1.2 2.2

Negative Threshold Temper-

ature Coefficient Q1 V_GS(TH) /

T_J 4.5 mV /

Q2 4.0 °C

Drain−to−Source On Resist-

ance Q1 R_DS(on) V_GS = 10 V I_D = 9 A 14 17.4

V_GS = 4.5 V I_D = 9 A 20 25 mW

Q2 V_GS = 10 V I_D = 11 A 11 13.3

V_GS = 4.5 V I_D = 11 A 16 20

Forward Transconductance Q1 g_FS V_DS = 1.5 V, I_D = 9 A 16 S

Q2 18

CHARGES, CAPACITANCES & GATE RESISTANCE

Input Capacitance Q1

C_ISS

V_GS = 0 V, f = 1 MHz, V_DS = 15 V

605

pF

Q2 660

Output Capacitance Q1

C_OSS 190

Q2 325

Reverse Capacitance Q1

C_RSS 102

Q2 17.5

5. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%

6. Switching characteristics are independent of operating junction temperatures.

(4)

ELECTRICAL CHARACTERISTICS (T_J = 25°C unless otherwise specified)

CHARGES, CAPACITANCES & GATE RESISTANCE

Total Gate Charge Q1

Q_G(TOT)

VGS = 4.5 V, VDS = 15 V; ID = 9 A

6.5

nC

Q2 5.0

Threshold Gate Charge Q1

QG(TH)

1.1

Q2 1.1

Gate−to−Source Charge Q1

QGS

1.9

Q2 2.0

Gate−to−Drain Charge Q1

QGD

3.2

Q2 1.46

Total Gate Charge Q1

Q_G(TOT) V_GS = 10 V, V_DS = 15 V; I_D = 9 A 12

Q2 10.6 nC

SWITCHING CHARACTERISTICS (Note 6) Turn−On Delay Time Q1

t_d(ON)

VGS = 4.5 V, VDS = 15 V, I_D = 9 A, R_G = 3.0 W

8.0

ns

Q2 7.5

Rise Time Q1

t_r 7.2

Q2 11.2

Turn−Off Delay Time Q1

t_d(OFF) 11

Q2 11.6

Fall Time Q1

t_f 3.3

Q2 1.9

SWITCHING CHARACTERISTICS (Note 6) Turn−On Delay Time Q1

t_d(ON)

V_GS = 10 V, V_DS = 15 V, ID = 9 A, RG = 3.0 W

4.2

ns

Q2 4.3

Rise Time Q1

t_r 11.6

Q2 11.4

Turn−Off Delay Time Q1

t_d(OFF) 14.1

Q2 14.3

Fall Time Q1

t_f 2.0

Q2 1.3

DRAIN−SOURCE DIODE CHARACTERISTICS

Forward Voltage

Q1

VSD

V_GS = 0 V, IS = 3 A

TJ = 25°C 0.80 1.2

TJ = 125°C 0.65 V

Q2 V_GS = 0 V,

IS = 2 A

TJ = 25°C 0.50 0.80

T_J = 125°C 0.45

(5)

ELECTRICAL CHARACTERISTICS (T_J = 25°C unless otherwise specified)

DRAIN−SOURCE DIODE CHARACTERISTICS Reverse Recovery Time Q1

t_RR

VGS = 0 V, dIS/dt = 100 A/ms, IS = 3 A

17.9

ns

Q2 23.3

Charge Time Q1

ta 9.0

Q2 11.3

Discharge Time Q1

tb 9.0

Q2 12

Reverse Recovery Charge Q1

QRR

8.0 nC

Q2 12

PACKAGE PARASITIC VALUES

Source Inductance Q1

LS

T_A = 25°C

0.36 nH

Q2 0.36

Drain Inductance Q1

L_D 0.054

Q2 0.054 nH

Gate Inductance Q1

L_G 1.3

Q2 1.3 nH

Gate Resistance Q1

R_G 0.8

Q2 0.8 W

ORDERING INFORMATION

Device Package Shipping^†

NTLLD4901NFTWG WDFN8

(Pb−Free) 3000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

(6)

TYPICAL CHARACTERISTICS − Q1

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics V_DS, DRAIN−TO−SOURCE VOLTAGE (V) V_GS, GATE−TO−SOURCE VOLTAGE (V)

5 4

3 2

1 00

10 20 25

5

4.0 3.0

2.0 1.5

01.0 5 10 25

Figure 3. On−Resistance vs. Gate−to−Source

Resistance Figure 4. On−Resistance vs. Drain Current and Gate Voltage

V_GS, GATE−TO−SOURCE VOLTAGE (V) I_D, DRAIN CURRENT (A)

9

8 10

7 6 5 4 102

20 25 30 40 45 55

30 25 20

10 5

130 14 15 17 20 22 23

Figure 5. On−Resistance Variation with

Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage

T_J, JUNCTION TEMPERATURE (°C) V_DS, DRAIN−TO−SOURCE VOLTAGE (V) 125

100 75 50 25 0

−25 0.5−50 1.2 1.4 1.6 1.7

30 25 20 15

10 1E−110

1E−10

ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A)

RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW) RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)

RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) IDSS, LEAKAGE (A)

15

V_GS = 2.2 V

3.0 V 3.2 V

2.8 V 7.5 V

10 V

T_J = 25°C V_DS = 5 V

T_J = 125°C

TJ = −55°C 15

20

15 35

50 ID = 10 A

15 19

T = 25°C VGS = 4.5 V

V_GS = 10 V

150 I_D = 9 A

V_GS = 10 V

0.8 1.0

T_J = 125°C TJ = 150°C 3

5 3.4 V

3.6 V 3.8 V

2.6 V 2.4 V 4.5 V thru 4 V

2.5 3.5

30

16 18 21

1.1 1.3 1.5

0.7 0.9

0.6

TJ = 25°C 1E−09

1E−08 1E−07 1E−06 1E−05

(7)

TYPICAL CHARACTERISTICS − Q1

Figure 7. Capacitance Variation Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge

V_DS, DRAIN−TO−SOURCE VOLTAGE (V) Qg, TOTAL GATE CHARGE (nC)

30 25

20 15

10 5

00 100 200 400 500 600 700 800

12 6

4 2

00 1 3 5 6 8 9

Figure 9. Resistive Switching Time Variation

vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current

RG, GATE RESISTANCE (W) V_SD, SOURCE−TO−DRAIN VOLTAGE (V)

100 10

11 10 100

0.9 0.8

0 0.3 0.4 0.5 0.6 0.7

0 1 2 3 4 5 6

C, CAPACITANCE (pF) VGS, GATE−TO−SOURCE VOLTAGE (V)

t, TIME (ns) IS, SOURCE CURRENT (A)

300

T_J = 25°C V_GS = 0 V C_iss

C_oss C_rss

8 10

2 4 7 10

I_D = 9 A T_J = 25°C V_GS = 4.5 V V_DD = 15 V QT

Qgs Qgd

VGS = 10 V VDD = 15 V ID = 10 A

t_d(off) t_d(on) t_f t_r

T_J = 25°C V_GS = 0 V 7

8 9

0.1 0.2

0.01 0.1 1 10 100

0.1 1 10 100

Figure 11. Maximum Rated Forward Biased Safe Operating Area

V_DS, DRAIN−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT VGS = 20 V

SINGLE PULSE TC = 25°C

1 ms 10 ms

10 ms dc 100 ms

1.0 1.1

Figure 12. Maximum Avalanche Energy vs.

Starting Junction Temperature T_J, STARTING JUNCTION TEMPERATURE (°C)

130 115

25 55 70 85 100

0 2 4 6 8 10

EAS, SINGLE PULSE DRAIN−TO− SOURCE AVALANCHE ENERGY (mJ)

ID = 9 A 12

14

40 145 160

(8)

TYPICAL CHARACTERISTICS − Q1

0.1 1 10 100

0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000

0.1 0.2

0.02 D = 0.5

0.05

0.01

SINGLE PULSE THERMAL RESISTANCE, RqJA(t) (°C/W)

t, PULSE TIME (sec) Figure 13. Thermal Response

(9)

TYPICAL CHARACTERISTICS − Q2

Figure 14. On−Region Characteristics Figure 15. Transfer Characteristics V_DS, DRAIN−TO−SOURCE VOLTAGE (V) V_GS, GATE−TO−SOURCE VOLTAGE (V)

5 4

3 2

1 00

10 20 25

5 30

3.5 3 2

01 10 15 30 40

Figure 16. On−Resistance vs. Gate−to−Source

Resistance Figure 17. On−Resistance vs. Drain Current and Gate Voltage

V_GS, GATE−TO−SOURCE VOLTAGE (V) I_D, DRAIN CURRENT (A)

9

8 10

7 6 5 4 02

30 40 60

30 25 20 10

5 80 10 12 14 18 20

Figure 18. On−Resistance Variation with

Temperature Figure 19. Drain−to−Source Leakage Current vs. Voltage

T_J, JUNCTION TEMPERATURE (°C) V_DS, DRAIN−TO−SOURCE VOLTAGE (V) 125

100 75 50 25 0

−25 0.6−50 1.2 1.4 1.6

30 25 20 15

10 1E−060

1E−05 1E−04 1E−02

ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A)

RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW) RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)

RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) IDSS, LEAKAGE (A)

15 35 40

V_GS = 2.2 V

3.0 V 2.8 V 7.5 V

10 V

T_J = 25°C V_DS = 5 V

T_J = 125°C

T_J = −55°C 20

25

10

ID = 10 A

15 35 40

16

VGS = 4.5 V

V_GS = 10 V

150 I_D = 11 A

V_GS = 10 V

0.8 1.0

VGS = 0 V TJ = 125°C TJ = 150°C 3

5 3.2 V

3.4 V

2.5 1.5

1E−03

TJ = 25°C 2.6 V

2.4 V 3.6 V 3.8 V

4.5 thru 4.0 V

5 35

20 50

4.5 4

T = 25°C

(10)

TYPICAL CHARACTERISTICS − Q2

Figure 20. Capacitance Variation Figure 21. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge

V_DS, DRAIN−TO−SOURCE VOLTAGE (V) Qg, TOTAL GATE CHARGE (nC)

30 25

20 15

10 5

10 100 1000

6 4

2 00

1 3 5 6 8 9

Figure 22. Resistive Switching Time Variation

vs. Gate Resistance Figure 23. Diode Forward Voltage vs. Current

RG, GATE RESISTANCE (W) V_SD, SOURCE−TO−DRAIN VOLTAGE (V)

100 10

11 10 100

0.9 0.8

0 0.3 0.4 0.5 0.6 0.7

0 1 2 3 4 5 6

C, CAPACITANCE (pF) VGS, GATE−TO−SOURCE VOLTAGE (V)

t, TIME (ns) IS, SOURCE CURRENT (A)

10

TJ = 25°C V_GS = 0 V

C_iss Coss

C_rss

8 10

2 4 7 10

ID = 9 A TJ = 25°C V_GS = 4.5 V V_DD = 15 V QT

Qgs Qgd

VGS = 10 V VDD = 15 V ID = 10 A

t_d(off)

t_d(on)

t_f t_r

T_J = 25°C V_GS = 0 V 7

8

0.1 0.2

0.01 0.1 1 10 100

0.1 1 10 100

Figure 24. Maximum Rated Forward Biased Safe Operating Area

V_DS, DRAIN−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)

RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0 V < VGS < 20 V

SINGLE PULSE TC = 25°C

1 ms 10 ms

10 ms

dc 100 ms

1.0

Figure 25. Maximum Avalanche Energy vs.

Starting Junction Temperature T_J, STARTING JUNCTION TEMPERATURE (°C)

130 115

25 55 70 85 100

0 2 4 6 8 10

EAS, SINGLE PULSE DRAIN−TO− SOURCE AVALANCHE ENERGY (mJ)

ID = 9.5 A 12

14

40 145 160

(11)

TYPICAL CHARACTERISTICS − Q2

0.01 0.1 1 10 100

0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000

0.1 0.2

0.02 D = 0.5

0.05 0.01

SINGLE PULSE THERMAL RESISTANCE, RqJA(t) (°C/W)

t, PULSE TIME (sec) Figure 26. Thermal Response

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WDFN8 3x3, 0.65P CASE 511BP

ISSUE B

DATE 17 JUL 2012 SCALE 2:1

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.05 AND 0.15 MM FROM TERMINAL TIP.

4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.

5. POSITIONAL TOLERANCE APPLIES TO ALL OF THE EXPOSED PADS.

ÇÇÇ

D A

E B

C 0.15

PIN ONE REFERENCE

TOP VIEW

SIDE VIEW

BOTTOM VIEW K D2

E2 C C

0.15

C 0.10

C

0.08 A1 _SEATING

PLANE

NOTE 3

b

8X

0.10 C 0.05 C

A B

DIM MILLIMETERSMIN MAX A 0.70 0.80 A1 0.00 0.05 b 0.30 0.50

D 3.00 BSC

D2 2.35 2.55

E 3.00 BSC

E2 0.90 1.10 e 0.65 BSC

L 0.20 0.40

1 4

8

*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

0.65PITCH 1.15

3.30

1

DIMENSIONS: MILLIMETERS

0.43

1

NOTE 4

0.50^5X

DETAIL A

A3 0.20 REF

A3

DETAIL B A

L1

DETAIL A L

ALTERNATE CONSTRUCTIONS

ÉÉ ÇÇ

A1ÇÇ

A3 L

ÇÇÇ ÉÉÉ

ÉÉÉ

DETAIL B

MOLD CMPD EXPOSED Cu

ALTERNATE CONSTRUCTIONS

L1 0.00 0.15

e

RECOMMENDED

G 0.43 BSC

5

2.60

GENERIC MARKING DIAGRAM*

XXXX = Specific Device Code A = Assembly Location

Y = Year

WW = Work Week G = Pb−Free Package

*This information is generic. Please refer to device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “ G”, may or may not be present.

XXXX AYWWG

G 1

E3 0.40 0.60

G2 0.68 BSC K 0.20 −−−

e/2

E3

G G2

A 0.10 M C B

M M

A 0.10 M C B

NOTE 5 NOTE 5

1.80

0.506X

0.68

0.65

(Note: Microdot may be in either location)

STYLE 1:

PIN 1. GATE 1 2. DRAIN 1 3. DRAIN 1 4. DRAIN 1 5. SOURCE 2 6. SOURCE 2 7. SOURCE 2 8. GATE 2 9. DRAIN 1 10. SOURCE 1/DRAIN 2

1.88

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

98AON53342E DOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 1 WDFN8, 3X3, 0.65P

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information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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