MOSFET – N-Channel, POWERTRENCH)

MOSFET – N-Channel, POWERTRENCH ⁾

40 V, 7.6 A, 29 mW

FDS8449, FDS8449-G

General Description

These N−Channel MOSFETs are produced using onsemi’s advanced POWERTRENCH process that has been especially tailored to minimize on−state resistance and yet maintain superior switching performance.

Features

• 7.6 A, 40 V R

= 29 m W @ V

= 10 V R

= 36 m W @ V

= 4.5 V

• High Power Handling Capability in a Widely Used Surface Mount Package

• Pb−Free, Halide Free and RoHS Compliant

T_A = 25°C unless otherwise noted.

Symbol Parameter Ratings Unit

VDSS Drain to Source Voltage 40 V

VGSS Gate to Source Voltage ±20 V

ID Drain Current

− Continuous(Note 1a)

− Pulsed 7.6

50

A

P_D Power Dissipation for Single Operation (Note 1a)

(Note 1b) 2.5

1

W

TJ, TSTG Operating and Storage Junction

Temperature Range −55 to +150 °C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

THERMAL CHARACTERISTICS

Symbol Parameter Ratings Unit

R_qJA Thermal Resistance,

Junction to Ambient (Note 1a) 50 °C/W

R_qJA Thermal Resistance,

Junction to Ambient (Note 1b) 125 °C/W

R_qJC Thermal Resistance,

Junction to Case (Note 1) 25 °C/W

MARKING DIAGRAM

Device Package Shipping^† ORDERING INFORMATION

FDS8449 SOIC8

(Pb−Free/

Halide Free)

2500 / Tape & Reel SOIC8

CASE 751EB

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.

FDS8449 = Specific Device Code

A = Assembly Site

L = Wafer Lot Number

YW = Assembly Start Week

$Y = onsemi Logo

&Z = Assembly Plant Code

&2 = 2−Digit Code Format

&K = 2−Digits Lot Run Traceability Code

FDS8449−G SOIC8

(Pb−Free/

Halide Free)

2500 / Tape & Reel 1

7 5

2 8

4

6 3

D D

D D

S G

S S

FDS8449

ALYW $Y&Z&2&K FDS 8449

FDS8449 FDS8449−G

ELECTRICAL CHARACTERISTICS TA = 25°C unless otherwise noted.

Symbol Parameter Test Conditions Min Typ Max Unit

DRAIN−SOURCE AVALANCHE RATINGS (Note 3)

E_AS Drain to Source Avalanche Energy V_DD = 40 V, I_D = 7.3 A, L = 1 mH − − 27 mJ

I_AS Drain to Source Avalanche Current − 7.3 − A

OFF CHARACTERISTICS

BV_DSS Drain to Source Breakdown Voltage I_D = 250 mA, VGS = 0 V 40 − − V

DBV_DSS DT_J

Breakdown Voltage Temperature

Coefficient ID = 250 mA,

Referenced to 25°C − 34 − mV/°C

I_DSS Zero Gate Voltage Drain Current V_DS = 32 V, V_GS = 0 V − − 1 mA

I_GSS Gate–Body Leakage V_GS = ±20 V, VDS = 0 V − − ±100 nA

ON CHARACTERISTICS (Note 2)

VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 mA 1 1.9 3 V

DV_GS(th) DT_J

Gate Threshold Voltage

Temperature Coefficient I_D = 250 mA, Referenced to 25°C − −5 − mV/°C

R_DS(on) Static Drain to Source On–Resistance ID = 7.6 A, VGS = 10 V, − 21 29 mW

I_D = 6.8 A, V_GS = 4.5 V − 26 36

ID = 7.6 A, VGS = 10 V,

T_J = 125°C − 29 43

g_FS Forward Transconductance V_DS = 10 V, I_D = 7.6 A − 21 − S

DYNAMIC CHARACTERISTICS

C_iss Input Capacitance VDS = 20 V, VGS = 0 V,

f = 1.0 MHz − 760 − pF

Coss Output Capacitance − 100 −

C_rss Reverse Transfer Capacitance − 60 −

R_G Gate Resistance f = 1.0 MHz − 1.2 − W

SWITCHING CHARACTERISTICS (Note 2)

t_d(on) Turn–On Delay Time VDD = 20 V, ID = 1 A,

V_GS = 10 V, R_GS = 6 W − 9 18 ns

t_r Turn–On Rise Time − 5 10

t_d(off) Turn–Off Delay Time − 23 17

tf Turn–Off Fall Time − 3 6

Q_g Total Gate Charge V_DS = 20 V, I_D = 7.6 A,

V_GS = 5 V − 7.7 11 nC

Q_gs Gate–Source Charge − 2.4 −

Q_gd Gate–Drain Charge − 2.8 −

DRAIN−SOURCE DIODE CHARACTERISTICS

VSD Drain to Source Diode Forward Voltage VGS = 0 V, IS = 2.1 A (Note 2) − 0.76 1.2 V t_rr Diode Reverse Recovery Time I_F = 7.6 A, d_IF/d_t = 100 A/ms − 17 − ns

Q_rr Diode Reverse Recovery Charge − 7 − nC

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

NOTES:

1. R_qJA is the sum of the junction−to−case and case−to−ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R_qJC is guaranteed by design while R_qCA is determined by the user’s board design.

a) 50°C/W when mounted

on a 1 in² pad of 2 oz. copper. b) 125°C/W when mounted on a minimum pad.

2. Pulse Test: Pulse Width < 300 ms, Duty Cycle < 2.0%

3. BV(avalanche) Single−Pulse rating is guaranteed if device is operated within the UIS SOA boundary of the device.

TYPICAL CHARACTERISTICS

Figure 1. On Region Characteristics Figure 2. On−Resistance Variation with Drain Current and Gate Voltage

0 0.5 1

0 4 20

8

I_D, Drain Current (A) RDS(ON), Normalized Drain to Source On−Resistance

V_DS, Drain to Source Voltage (V) ID, Drain Current (A)

0 4 8

0.6 1 1.4 2.2 1.8

V_GS, Gate to Source Voltage (V) RDS(on), On−Resistance (W)

6

2 4 8 10

0.05

0.07 ID = 3.5 A

20

Figure 3. On−Resistance Variation with Temperature

−50 −25 0 25 50 125 150

T_J, Junction Temperature (°C) RDS(ON), Normalized Drain to Source On−Resistance

Figure 4. On−Resistance Variation with Gate−to−Source Voltage

VSD, Body Diode Forward Voltage (V) IS, Reverse Drain Current (A)

0.4

0 0.2 0.6

0.1 1 10 100

Figure 5. Transfer Characteristics

1 1.5 2 2.5 3.5

0 5 10 15 20

Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature 2

ID, Drain Current (A)

V_GS, Gate to Source Voltage (V)

0.01 0.001

0.8 1.0 1.2

2.5 12

T_A = 25°C 0.06

25°C 12

16

16 2.6

3

3 1.5

6.0 V 4.5 V

4.0 V 3.5 V

3.0 V

V_GS = 10 V V_GS = 3.0 V

3.5 V

4.0 V 4.5 V

6.0 V

10 V

0.6 0.8 1 1.2 1.4 1.6

75 100 I_D = 7.6 A

V_GS = −10 V

0.04 0.03 0.02 0.01

T_A = 125°C

V_DS = 10 V

T_A = 125°C −55°C

0.0001

V_GS = 0 V

T_A = 125°C

25°C

−55°C

TYPICAL CHARACTERISTICS

Figure 7. Gate Charge Characteristics Figure 8. Capacitance Characteristics

0 4 16

0 2

VDS, Drain to Source Voltage (V)

Capacitance (pF)

Q_g, Gate Charge (nC) VGS, Gate−Source Voltage (V)

4 8 6

0 400

0 15

Figure 9. Maximum Safe Operating Area 0.010.1

t1, Time (s) VDS, Drain−Source Voltage (V)

ID, Drain Current (A) 1 10

0 40

0.001 0.01 0.1

Figure 10. Single Pulse Maximum Power Dissipation

10 8

10 1000

30

50

1000

P(pk), Peak Transient Power (W)

12 ID = 7.6 A

20 V

C_iss

Coss

C_rss

Figure 11. Single Pulse Maximum Peak Current 0.001

20

tAV, Time in Avalanche (ms) 1

0.01

Figure 12. Unclamped Inductive Switching Capability

I(AS), Avalanche Current (A)

1 10

100

0.1

100

0.01 1 10 100 1000

30 40 50

0.1 1 10

10 100 V_DS = 10 V 30 V

800

600

200

5 10 20 25 35 40

f = 1 MHz V_GS = 0 V

100 RDS(ON) LIMIT

V_GS = 10 V Single Pulse R_qJA = 125°C/W T_A = 25°C

DC10 s1 s

100 ms10 ms1 ms100 ms Single Pulse

R_qJA = 125°C/W T_A = 25°C

1 30

20

10

10

0 0.1

Single Pulse R_qJA = 125°C/W T_A = 25°C

t1, Time (s)

I(pk), Peak Transient Current (A)

T_J = 25°C

TYPICAL CHARACTERISTICS

Figure 13. Transient Thermal Response Curve 0.001

0.01

t₁,Time (s) r(t), Normalized Effective Transient Thermal Resistance

0.1 1

0.01 0.1 1 10 100 1000

0.0001 0.001

t₁ t₂ P_DM

T_J − T_A = P × R_qJA(t) Duty Factor D = t₁ / t₂ R_qJA(t) = r(t) × RqJA

R_qJA = 125°C/W D = 0.5

0.2 0.1 0.05 0.02 0.01

Single Pulse

NOTE: Transient thermal response will change depending on the circuit board design.

POWERTRENCH is a registered trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries.

SOIC8 CASE 751EB

ISSUE A

DATE 24 AUG 2017

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

98AON13735G DOCUMENT NUMBER:

DESCRIPTION:

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Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 1 SOIC8

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