NTMFS4943N Power MOSFET

Power MOSFET

30 V, 41 A, Single N−Channel, SO−8 FL

Features

• ^{Low R}

to Minimize Conduction Losses

• Low Capacitance to Minimize Driver Losses

• Optimized Gate Charge to Minimize Switching Losses

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant

Applications

• CPU Power Delivery

• DC−DC Converters

MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)

Parameter Symbol Value Unit

Drain−to−Source Voltage V_DSS 30 V

Gate−to−Source Voltage V_GS ±20 V

Continuous Drain Current R_qJA (Note 1)

Steady State

T_A = 25°C I_D 14 A

T_A = 100°C 8.7

Power Dissipation

R_qJA (Note 1) T_A = 25°C P_D 2.6 W

Continuous Drain Current R_qJA ≤ 10 s (Note 1)

T_A = 25°C ID 23 A

T_A = 100°C 14.3 Power Dissipation

R_qJA ≤ 10 s (Note 1)

TA = 25°C PD 6.83 W

Continuous Drain Current R_qJA (Note 2)

TA = 25°C I_D 8.3 A

TA = 100°C 5.2

Power Dissipation

R_qJA (Note 2) T_A = 25°C P_D 0.91 W

Continuous Drain Current R_qJC (Note 1)

T_C = 25°C I_D 41 A

T_C = 85°C 26

Power Dissipation

R_qJC (Note 1) T_C = 25°C P_D 22.3 W

Pulsed Drain

Current T_A = 25°C, t_p = 10 ms I_DM 125 A Current Limited by Package T_A = 25°C I_Dmax 100 A Operating Junction and Storage

Temperature TJ,

T_STG −55 to

+150 °C

Source Current (Body Diode) I_S 20 A

Drain to Source DV/DT dV/dt 8.0 V/ns

Single Pulse Drain−to−Source Avalanche Energy TJ = 25°C, VDD = 30 V, VGS = 10 V, I_L = 25 A_pk, L = 0.1 mH, R_G = 25 W

E_AS 31 mJ

Lead Temperature for Soldering Purposes

(1/8″ from case for 10 s) T_L 260 °C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.

2. Surface−mounted on FR4 board using the minimum recommended pad size.

SO−8 FLAT LEAD CASE 488AA

STYLE 1

MARKING DIAGRAM http://onsemi.com

A = Assembly Location

Y = Year

W = Work Week ZZ = Lot Traceability

4943N AYWZZ

1

V_(BR)DSS R_DS(ON) MAX I_D MAX 30 V 7.2 mW @ 10 V

11 mW @ 4.5 V 41 A

G (4)

S (1,2,3) N−CHANNEL MOSFET

D (5,6)

Device Package Shipping^† ORDERING INFORMATION

NTMFS4943NT1G SO−8 FL

(Pb−Free) 1500 / Tape & Reel NTMFS4943NT3G SO−8 FL

(Pb−Free) 5000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

S S S G

D

D D

D

http://onsemi.com 2

THERMAL RESISTANCE MAXIMUM RATINGS

Parameter Symbol Value Unit

Junction−to−Case (Drain) R_qJC 5.6

Junction−to−Ambient – Steady State (Note 3) R_qJA 49.1 °C/W

Junction−to−Ambient – Steady State (Note 4) R_qJA 137.2

Junction−to−Ambient – (t ≤ 10 s) (Note 3) R_qJA 18.3

3. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.

4. Surface−mounted on FR4 board using the minimum recommended pad size.

ELECTRICAL CHARACTERISTICS (T_J = 25°C unless otherwise specified)

Parameter Symbol Test Condition Min Typ Max Unit

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage V(BR)DSS V_GS = 0 V, I_D = 250 mA 30 V

Drain−to−Source Breakdown Voltage

(transient) V(BR)DSSt VGS = 0 V, ID(aval) = 10.5 A,

T_case = 25°C, ttransient = 100 ns 34 V Drain−to−Source Breakdown Voltage

Temperature Coefficient V_(BR)DSS/

T_J 15 mV/°C

Zero Gate Voltage Drain Current I_DSS V_GS = 0 V,

VDS = 24 V T_J = 25°C 1.0

mA

T_J = 125°C 10

Gate−to−Source Leakage Current IGSS VDS = 0 V, VGS = ±20 V ±100 nA

ON CHARACTERISTICS (Note 5)

Gate Threshold Voltage VGS(TH) V_GS = V_DS, I_D = 250 mA 1.2 1.66 2.2 V

Negative Threshold Temperature Coefficient VGS(TH)/TJ 4.0 mV/°C

Drain−to−Source On Resistance R_DS(on) V_GS = 10 V ID = 30 A 5.8 7.2

ID = 15 A 5.8 mW

VGS = 4.5 V ID = 30 A 8.2 11

I_D = 15 A 8.2

Forward Transconductance g_FS V_DS = 1.5 V, I_D = 15 A 32 S

CHARGES, CAPACITANCES & GATE RESISTANCE

Input Capacitance C_ISS

V_GS = 0 V, f = 1 MHz, V_DS = 15 V

1401

Output Capacitance C_OSS 446 pF

Reverse Transfer Capacitance C_RSS 16

Capacitance Ratio C_RSS /

C_ISS V_GS = 0 V, V_DS = 15 V, f = 1 MHz 0.011 0.023

Total Gate Charge QG(TOT)

V_GS = 4.5 V, V_DS = 15 V; I_D = 30 A

9.2

Threshold Gate Charge QG(TH) 2.7 nC

Gate−to−Source Charge QGS 4.4

Gate−to−Drain Charge QGD 1.9

Total Gate Charge Q_G(TOT) V_GS = 10 V, V_DS = 15 V; I_D = 30 A 20.9 nC

SWITCHING CHARACTERISTICS (Note 6)

Turn−On Delay Time t_d(ON)

V_GS = 4.5 V, V_DS = 15 V, I_D = 15 A, R_G = 3.0 W

11

Rise Time t_r 31 ns

Turn−Off Delay Time t_d(OFF) 18

Fall Time t_f 3.0

5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.

6. Switching characteristics are independent of operating junction temperatures.

ELECTRICAL CHARACTERISTICS (T_J = 25°C unless otherwise specified)

Parameter Symbol Test Condition Min Typ Max Unit

SWITCHING CHARACTERISTICS (Note 6)

Turn−On Delay Time td(ON)

V_GS = 10 V, V_DS = 15 V, I_D = 15 A, R_G = 3.0 W

8.0

Rise Time t_r 21 ns

Turn−Off Delay Time t_d(OFF) 21

Fall Time t_f 2.1

DRAIN−SOURCE DIODE CHARACTERISTICS

Forward Diode Voltage V_SD VGS = 0 V,

I_S = 30 A

T_J = 25°C 0.9 1.1

T_J = 125°C 0.8 V

Reverse Recovery Time t_RR

V_GS = 0 V, dIS/dt = 100 A/ms, I_S = 30 A

23

Charge Time t_a 12.5 ns

Discharge Time t_b 10.5

Reverse Recovery Charge Q_RR 10 nC

PACKAGE PARASITIC VALUES

Source Inductance L_S

T_A = 25°C

0.93 nH

Drain Inductance L_D 0.005 nH

Gate Inductance L_G 1.84 nH

Gate Resistance RG 1.1 2.0 W

5. Pulse Test: pulse width v 300 ms, duty cycle v 2%.

6. Switching characteristics are independent of operating junction temperatures.

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TYPICAL CHARACTERISTICS

4.5 V 10 V

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics V_DS, DRAIN−TO−SOURCE VOLTAGE (V) V_GS, GATE−TO−SOURCE VOLTAGE (V)

4 3

2 1

00 20 40 60

30 70

4.0 3.5 3.0

2.0 1.5

01.0 20 40 60

Figure 3. On−Resistance vs. V_GS Figure 4. On−Resistance vs. Drain Current and Gate Voltage

V_GS (V) I_D, DRAIN CURRENT (A)

9.0 8.0

7.0 10

6.0 5.0 4.0 0.0053.0

0.007 0.009 0.010

70 50

30 40 60 80

0.00420 0.005 0.007 0.008 0.009

Figure 5. On−Resistance Variation with

Temperature Figure 6. Drain−to−Source Leakage Current vs. Voltage

T_J, JUNCTION TEMPERATURE (°C) V_DS, DRAIN−TO−SOURCE VOLTAGE (V) 150

125 100 75 25

0

−25

−50 0.8 1.0 1.2 1.3 1.5 1.6 1.7

30 25

20 15

10 105

100 1000 10,000

ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A)

RDS(on), DRAIN−TO−SOURCE RESISTANCE (W) RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)

RDS(on), DRAIN−TO−SOURCE RES- ISTANCE (NORMALIZED) IDSS, LEAKAGE (nA)

80

10

4.0 V

7 V 4.2 V 3.8 V

3.6 V 3.4 V 3.2 V 3.0 V 2.8 V 2.6 V 2.4 V

TJ = 25°C V_DS = 10 V

T_J = 25°C

T_J = 125°C

TJ = −55°C

0.008

0.006 I_D = 30 A

T_J = 25°C

V_GS = 4.5 V TJ = 25°C

VGS = 10 V

50 I_D = 30 A

V_GS = 10 V

V_GS = 0 V

T_J = 85°C TJ = 150°C

T_J = 125°C 2.5 80

10 70

0.006 0.012 0.011

0.9 1.1 1.4 1.8

0.010 0.012 0.011

0.6 0.7 1.9 50

30 50

0.013 0.014

TYPICAL CHARACTERISTICS

Figure 7. Capacitance Variation Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge

V_DS, DRAIN−TO−SOURCE VOLTAGE (V) Qg, TOTAL GATE CHARGE (nC)

25 20

15

10 30

5 00

200 800 1000

18 14

12 10 8 4

2 00 1 2 4 6 7 8 11

Figure 9. Resistive Switching Time Variation

vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current

RG, GATE RESISTANCE (W) V_SD, SOURCE−TO−DRAIN VOLTAGE (V)

100 10

11 10 100 1000

0.9 0.8

0.7 1.0

0.6 0.5

00.4 5 10 15 20 25 30

Figure 11. Maximum Rated Forward Biased

Safe Operating Area Figure 12. Maximum Avalanche Energy vs.

Starting Junction Temperature V_DS, DRAIN−TO−SOURCE VOLTAGE (V) T_J, STARTING JUNCTION TEMPERATURE (°C)

100 10

1 0.10.1

1 10 100 1000

150 125

100 75

50 025

5 20 30

C, CAPACITANCE (pF) VGS, GATE−TO−SOURCE VOLTAGE (V)

t, TIME (ns) IS, SOURCE CURRENT (A)

ID, DRAIN CURRENT (A) EAS, SINGLE PULSE DRAIN−TO− SOURCE AVALANCHE ENERGY (mJ)

V_GS = 0 V T_J = 25°C C_iss

C_oss

C_rss

6 16

3 5 10

T_J = 25°C

QT

Qgs Qgd

V_DD = 15 V V_GS = 10 V I_D = 30 A

V_DD = 15 V I_D = 15 A V_GS = 10 V

t_d(off)

t_d(on) t_r tf

TJ = 25°C T_J = 125°C

V_GS = 0 V

V_GS = 20 V Single Pulse T_C = 25°C

R_DS(on) Limit Thermal Limit Package Limit

100 ms

10 ms 1 ms

dc

ID = 25 A 1400

1800

10 15 25 35 400

600 1200 1600

20 9

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TYPICAL CHARACTERISTICS

Figure 13. Thermal Response PULSE TIME (sec)

0.01 0.001

0.0001 0.00001

0.000001 0.01

0.1 1 10 100

R(t) (°C/W)

0.1 1 10 100 1000

10%

Duty Cycle = 50%

20%

5%

2%

1%

Single Pulse

Figure 14. GFS vs. ID ID (A)

40 30 10

00 10 20 30 40 50 70

GFS (S)

20 50

60

60 70 80

M 3.00 3.40 q 0 _ −−− ^3.8012 _ DFN5 5x6, 1.27P

(SO−8FL) CASE 488AA

ISSUE N

DATE 25 JUN 2018 SCALE 2:1

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH PROTRUSIONS OR GATE BURRS.

XXXXXX = Specific Device Code A = Assembly Location

Y = Year

W = Work Week

ZZ = Lot Traceability

1 2 3 4

TOP VIEW

SIDE VIEW

BOTTOM VIEW D1

E1 q

D

E 2

2 B A

0.20 C

0.20 C

2 X

2 X

DIM MIN NOM MILLIMETERS A 0.90 1.00 A1 0.00 −−−

b 0.33 0.41 c 0.23 0.28

D 5.15

D1 4.70 4.90 D2 3.80 4.00

E 6.15

E1 5.70 5.90 E2 3.45 3.65

e 1.27 BSC

G 0.51 0.575

K 1.20 1.35

L 0.51 0.575

L1 0.125 REF

A 0.10 C

0.10 C

DETAIL A

1 4

L1 e/2

8X

G D2 E2

K b

A 0.10 C B 0.05 c

L

DETAIL A c A1

4 X

C

SEATING PLANE

GENERIC MARKING DIAGRAM*

1

XXXXXX AYWZZ 1

MAX 1.10 0.05 0.51 0.33 5.10 4.20 6.10 3.85 0.71 1.50 0.71

STYLE 1:

PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN

M

*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

1.270

2X

0.750 1.000 0.905

4.530 1.530

4.560 0.495

3.200

1.330

0.965

2X 2X

4X 4X PIN 5

(EXPOSED PAD)

STYLE 2:

PIN 1. ANODE 2. ANODE 3. ANODE 4. NO CONNECT 5. CATHODE

5.00 5.30

6.00 6.30

PITCH

DIMENSIONS: MILLIMETERS

1

RECOMMENDED e

2X

0.475

*This information is generic. Please refer to device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Some products may not follow the Generic Marking.

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

98AON14036D DOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 1 DFN5 5x6, 1.27P (SO−8FL)

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