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4.3 Multiplexing Characteristics

4.4.26 System and Miscellaneous

4.4.26.1 Sysboot

注: For more information, see the Initialization (ROM Code) section of the device TRM.

4-29. Sysboot Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL

sysboot0 Boot Mode Configuration 0. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device.

I M6

sysboot1 Boot Mode Configuration 1. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device.

I M2

sysboot2 Boot Mode Configuration 2. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device.

I L5

sysboot3 Boot Mode Configuration 3. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device.

I M1

sysboot4 Boot Mode Configuration 4. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device.

I L6

sysboot5 Boot Mode Configuration 5. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device.

I L4

sysboot6 Boot Mode Configuration 6. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device.

I L3

sysboot7 Boot Mode Configuration 7. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device.

I L2

sysboot8 Boot Mode Configuration 8. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device.

I L1

sysboot9 Boot Mode Configuration 9. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device.

I K2

sysboot10 Boot Mode Configuration 10. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device.

I J1

sysboot11 Boot Mode Configuration 11. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device.

I J2

sysboot12 Boot Mode Configuration 12. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device.

I H1

sysboot13 Boot Mode Configuration 13. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device.

I J3

sysboot14 Boot Mode Configuration 14. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device.

I H2

sysboot15 Boot Mode Configuration 15. The value latched on this pin upon porz reset release will determine the boot mode configuration of the device.

I H3

4.4.26.2 Power, Reset, and Clock Management (PRCM)

注: For more information, see PRCM section of the device TRM.

4-30. PRCM Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL

clkout1 Device Clock output 1. Can be used externally for devices with non-critical timing requirements, or for debug, or as a reference clock on GPMC as described in

7-25GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Defaultand7-27GPMC/NOR Flash Interface Switching Characteristics -Synchronous Mode - Alternate.

O F21/P7

clkout2 Device Clock output 2. Can be used externally for devices with non-critical timing requirements, or for debug.

O D18/N1

clkout3 Device Clock output 3. Can be used externally for devices with non-critical timing requirements, or for debug.

O C23

rstoutn Reset out (Active low).This pin asserts low in response to any global reset condition on the device.(2)

O F23

resetn Device Reset Input I E23

porz Power on Reset (active low).This pin must be asserted low until all device supplies are valid (see reset sequence/requirements)

I F22

xref_clk0 External Reference Clock 0. For Audio and other Peripherals. I D18 xref_clk1 External Reference Clock 1. For Audio and other Peripherals. I E17 xref_clk2 External Reference Clock 2. For Audio and other Peripherals. I B26 xref_clk3 External Reference Clock 3. For Audio and other Peripherals. I C23

xi_osc0 System Oscillator OSC0 Crystal input / LVCMOS clock input.Functions as the input connection to a crystal when the internal oscillator OSC0 is used. Functions as an LVCMOS-compatible input clock when an external oscillator is used.

I AE15

xo_osc0 System Oscillator OSC0 Crystal output O AD15

xi_osc1 Auxiliary Oscillator OSC1 Crystal input / LVCMOS clock input.Functions as the input connection to a crystal when the internal oscillator OSC1 is used. Functions as an LVCMOS-compatible input clock when an external oscillator is used

I AC15

xo_osc1 Auxiliary Oscillator OSC1 Crystal output O AC13

RMII_MHZ_50_CL K(1)

RMII Reference Clock (50MHz).This pin is an input when external reference is used or output when internal reference is used.

IO U3

(1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between VIHand VILmust be less than VHYS. (2) Note that rstoutn is only valid after vddshv3 is valid. If the rstoutn signal will be used as a reset into other devices attached to the SOC, it

must be AND'ed with porz. This will prevent glitches occurring during supply ramping being propagated.

4.4.26.3 Real-Time Clock (RTC) Interface

注: For more information, see the Real-Time Clock (RTC) chapter of the device TRM.

注: RTC only mode is not supported feature.

4-31. RTC Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL

Wakeup0 RTC External Wakeup Input 0 I AD17

Wakeup3 RTC External Wakeup Input 3 I AC16

rtc_porz RTC Power Domain Power-On Reset Input I AB17

rtc_osc_xi_clkin32 RTC Oscillator Input. Crystal connection to internal RTC oscillator. Functions as an RTC clock input when an external oscillator is used.

I AE14

rtc_osc_xo RTC Oscillator Output O AD14

rtc_iso(1) RTC Domain Isolation Signal I AF14

on_off RTC Power Enable output pin O Y11

(1) This signal must be kept 0 if device power supplies are not valid during RTC mode and 1 during normal operation. This can typically be achieved by connecting rtc_iso to the same signal driving porz (not rtc_porz) with appropriate voltage level translation if necessary.

4.4.26.4 System Direct Memory Access (SDMA)

注: For more information, see the DMA Controllers / System DMA section of the device TRM.

4-32. SDMA Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL

dma_evt1 System DMA Event Input 1 I P7/P4

dma_evt2 System DMA Event Input 2 I N1/R3

dma_evt3 System DMA Event Input 3 I N6

dma_evt4 System DMA Event Input 4 I M4

4.4.26.5 Interrupt Controllers (INTC)

注: For more information, see the Interrupt Controllers section of the device TRM.

nmin_dsp Non maskable interrupt input, active-low. This pin can be optionally routed to the DSP NMI input or as generic input to the Arm cores. Note that by default this pin has an internal pulldown resistor enabled. This internal pulldown should be disabled or countered by a stronger external pullup resistor before routing to the DSP or Arm processors.

I D21

sys_nirq2 External interrupt event to any device INTC I AD17

sys_nirq1 External interrupt event to any device INTC I AC16

4.4.26.6 Observability

:

For more information, see the Control Module section of the device TRM.

4-34. Observability Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL

obs0 Observation Output 0 O F10

obs1 Observation Output 1 O G11

obs2 Observation Output 2 O E9

obs3 Observation Output 3 O F9

obs4 Observation Output 4 O F8

obs5 Observation Output 5 O D7

obs6 Observation Output 6 O D8

obs7 Observation Output 7 O A5

obs8 Observation Output 8 O C6

obs9 Observation Output 9 O C8

obs10 Observation Output 10 O C7

obs11 Observation Output 11 O A7

obs12 Observation Output 12 O A8

obs13 Observation Output 13 O C9

obs14 Observation Output 14 O A9

obs15 Observation Output 15 O B9

obs16 Observation Output 16 O F10

obs17 Observation Output 17 O G11

obs18 Observation Output 18 O E9

obs19 Observation Output 19 O F9

obs20 Observation Output 20 O F8

obs21 Observation Output 21 O D7

obs22 Observation Output 22 O D8

obs23 Observation Output 23 O A5

obs24 Observation Output 24 O C6

obs25 Observation Output 25 O C8

obs26 Observation Output 26 O C7

obs27 Observation Output 27 O A7

obs28 Observation Output 28 O A8

obs29 Observation Output 29 O C9

obs30 Observation Output 30 O A9

obs31 Observation Output 31 O B9

obs_dmarq1 DMA Request External Observation Output 1 O G11

obs_dmarq2 DMA Request External Observation Output 2 O D8

obs_irq1 IRQ External Observation Output 1 O F10

obs_irq2 IRQ External Observation Output 2 O D7

4.4.27 Power Supplies