Recommended Operating Conditions

In document AM571x Sitaraプロセッサシリコン・リビジョン2.0 datasheet (Rev. G) (Page 141-145)

The device is used under the recommended operating conditions described in

5-5.

注: Logic functions and parameter values are not assured out of the range specified in the recommended operating conditions.

5-5. Recommended Operating Conditions

PARAMETER DESCRIPTION MIN(2) NOM MAX DC(3) MAX(2) UNIT

Input Power Supply Voltage Range

vdd Core voltage domain supply See 5.5 V

vdd_mpu Supply voltage range for MPU domain See 5.5 V

vdd_gpu GPU voltage domain supply See 5.5 V

vdd_dsp DSP voltage domain supply See 5.5 V

vdd_iva IVA voltage domain supply See 5.5 V

vdd_rtc RTC voltage domain supply See 5.5 V

vdda_usb1 DPLL_USB and HS USB1 1.8V analog power supply

1.71 1.80 1.836 1.89 V

Maximum noise (peak-peak) 50 mVPPmax

vdda_usb2 HS USB2 1.8V analog power supply 1.71 1.80 1.836 1.89 V

Maximum noise (peak-peak) 50 mVPPmax

vdda33v_usb1 HS USB1 3.3V analog power supply.If USB1 is not used, this pin can alternatively be connected to VSS if the following requirements are met:

- The usb1_dm/usb1_dp pins are left unconnected

- The USB1 PHY is kept powered down

3.135 3.3 3.366 3.465 V

Maximum noise (peak-peak) 50 mVPPmax

vdda33v_usb2 HS USB2 3.3V analog power supply. If USB2 is not used, this pin can alternatively be connected to VSS if the following requirements are met:

- The usb2_dm/usb2_dp pins are left unconnected

- The USB2 PHY is kept powered down

3.135 3.3 3.366 3.465 V

Maximum noise (peak-peak) 50 mVPPmax

vdda_per PER PLL and PER HSDIVIDER analog power supply

1.71 1.80 1.836 1.89 V

Maximum noise (peak-peak) 50 mVPPmax

vdda_ddr DPLL_DDR and DDR HSDIVIDER

analog power supply

1.71 1.80 1.836 1.89 V

Maximum noise (peak-peak) 50 mVPPmax

vdda_debug DPLL_DEBUG analog power supply 1.71 1.80 1.836 1.89 V

Maximum noise (peak-peak) 50 mVPPmax

vdda_dsp_iva DPLL_DSP and DPLL_IVA analog power supply

1.71 1.80 1.836 1.89 V

Maximum noise (peak-peak) 50 mVPPmax

vdda_core_gmac DPLL_CORE and CORE HSDIVIDER analog power supply

1.71 1.80 1.836 1.89 V

Maximum noise (peak-peak) 50 mVPPmax

vdda_pll_spare DPLL_SPARE analog power supply 1.71 1.80 1.836 1.89 V

Maximum noise (peak-peak) 50 mVPPmax

vdda_gpu DPLL_GPU analog power supply 1.71 1.80 1.836 1.89 V

Maximum noise (peak-peak) 50 mVPPmax

vdda_hdmi PLL_HDMI and HDMI analog power supply

1.71 1.80 1.836 1.89 V

Maximum noise (peak-peak) 50 mVPPmax

vdda_pcie DPLL_PCIe_REF and PCIe analog power supply

1.71 1.80 1.836 1.89 V

Maximum noise (peak-peak) 50 mVPPmax

vdda_pcie0 PCIe ch0 RX/TX analog power supply 1.71 1.80 1.89 V

Maximum noise (peak-peak) 50 mVPPmax

vdda_sata DPLL_SATA and SATA RX/TX analog power supply

1.71 1.80 1.836 1.89 V

Maximum noise (peak-peak) 50 mVPPmax

vdda_usb3 DPLL_USB_OTG_SS and USB3.0 RX/TX analog power supply

1.71 1.80 1.836 1.89 V

Maximum noise (peak-peak) 50 mVPPmax

vdda_video DPLL_VIDEO1 analog power supply 1.71 1.80 1.836 1.89 V

Maximum noise (peak-peak) 50 mVPPmax

vdds_mlbp MLBP IO power supply 1.71 1.80 1.89 V

Maximum noise (peak-peak) 50 mVPPmax

vdda_mpu_abe DPLL_MPU analog power supply 1.71 1.80 1.836 1.89 V

Maximum noise (peak-peak) 50 mVPPmax

vdda_osc HFOSC analog power supply 1.71 1.80 1.89 V

Maximum noise (peak-peak) 50 mVPPmax

vdda_rtc RTC bias and RTC LFOSC analog power supply

1.71 1.80 1.89 V

Maximum noise (peak-peak) 50 mVPPmax

vdda_csi CSI Interface 1.8v Supply 1.71 1.80 1.836 1.89 V

Maximum noise (peak-peak) 50 mVPPmax

vdds18v 1.8V power supply 1.71 1.80 1.836 1.89 V

Maximum noise (peak-peak) 50 mVPPmax

vdds18v_ddr1 EMIF1 bias power supply 1.71 1.80 1.836 1.89 V

Maximum noise (peak-peak) 50 mVPPmax

vdds_ddr1 EMIF1 power supply (1.5V for DDR3 mode / 1.35V DDR3L mode)

1.35-V Mode

1.28 1.35 1.377 1.42 V

1.5-V Mode 1.43 1.50 1.53 1.57

Maximum noise (peak-peak)

1.35-V Mode

50 mVPPmax

1.5-V Mode vddshv5 Dual Voltage (1.8V or

3.3V) power supply for the RTC Power Group pins

1.8-V Mode 1.71 1.80 1.836 1.89 V

3.3-V Mode 3.135 3.30 3.366 3.465

Maximum noise (peak-peak)

1.8-V Mode 50 mVPPmax

3.3-V Mode vddshv1 Dual Voltage (1.8V or

3.3V) power supply for the VIN2 Power Group pins

1.8-V Mode 1.71 1.80 1.836 1.89 V

3.3-V Mode 3.135 3.30 3.366 3.465

Maximum noise (peak-peak)

1.8-V Mode 50 mVPPmax

3.3-V Mode vddshv10 Dual Voltage (1.8V or

3.3V) power supply for the GPMC Power Group pins

1.8-V Mode 1.71 1.80 1.836 1.89 V

3.3-V Mode 3.135 3.30 3.366 3.465

Maximum noise (peak-peak)

1.8-V Mode 50 mVPPmax

3.3-V Mode vddshv11 Dual Voltage (1.8V or

3.3V) power supply for the MMC2 Power Group pins

1.8-V Mode 1.71 1.80 1.836 1.89 V

3.3-V Mode 3.135 3.30 3.366 3.465

Maximum noise (peak-peak)

1.8-V Mode 50 mVPPmax

3.3-V Mode

vddshv2 Dual Voltage (1.8V or 3.3V) power supply for the VOUT Power Group pins

1.8-V Mode 1.71 1.80 1.836 1.89 V

3.3-V Mode 3.135 3.30 3.366 3.465

Maximum noise (peak-peak)

1.8-V Mode 50 mVPPmax

3.3-V Mode vddshv3 Dual Voltage (1.8V or

3.3V) power supply for the GENERAL Power Group pins

1.8-V Mode 1.71 1.80 1.836 1.89 V

3.3-V Mode 3.135 3.30 3.366 3.465

Maximum noise (peak-peak)

1.8-V Mode 50 mVPPmax

3.3-V Mode vddshv4 Dual Voltage (1.8V or

3.3V) power supply for the MMC4 Power Group pins

1.8-V Mode 1.71 1.80 1.836 1.89 V

3.3-V Mode 3.135 3.30 3.366 3.465

Maximum noise (peak-peak)

1.8-V Mode 50 mVPPmax

3.3-V Mode vddshv6 Dual Voltage (1.8V or

3.3V) power supply for the VIN1 Power Group pins

1.8-V Mode 1.71 1.80 1.836 1.89 V

3.3-V Mode 3.135 3.30 3.366 3.465

Maximum noise (peak-peak)

1.8-V Mode 50 mVPPmax

3.3-V Mode vddshv7 Dual Voltage (1.8V or

3.3V) power supply for the WIFI Power Group pins

1.8-V Mode 1.71 1.80 1.836 1.89 V

3.3-V Mode 3.135 3.30 3.366 3.465

Maximum noise (peak-peak)

1.8-V Mode 50 mVPPmax

3.3-V Mode vddshv8 Dual Voltage (1.8V or

3.3V) power supply for the MMC1 Power Group pins

1.8-V Mode 1.71 1.80 1.836 1.89 V

3.3-V Mode 3.135 3.30 3.366 3.465

Maximum noise (peak-peak)

1.8-V Mode 50 mVPPmax

3.3-V Mode vddshv9 Dual Voltage (1.8V or

3.3V) power supply for the RGMII Power Group pins

1.8-V Mode 1.71 1.80 1.836 1.89 V

3.3-V Mode 3.135 3.30 3.366 3.465

Maximum noise (peak-peak)

1.8-V Mode 50 mVPPmax

3.3-V Mode

vss Ground supply 0 V

vssa_hdmi DPLL_HDMI and HDMI PHY analog ground

0 V

vssa_pcie PCIe analog ground 0 V

vssa_usb HS USB1 and HS USB2 analog ground 0 V

vssa_usb3 DPLL_USB and USB3.0 RX/TX analog ground

0 V

vssa_csi CSI Interface 0v Supply 0 V

vssa_sata SATA TX ground 0 V

vssa_video DPLL_VIDEO1 analog ground 0 V

vssa_osc0 OSC0 analog ground 0 V

vssa_osc1 OSC1 analog ground 0 V

TJ Operating junction temperature range

Commercial 0 90 °C

Extended -40 105

Automotive -40 125

ddr1_vref0 Reference Power Supply EMIF1 0.5*vdds_ddr1 V

(1) Refer to Power on Hours table for limitations.

(2) The voltage at the device ball should never be below the MIN voltage or above the MAX voltage for any amount of time. This requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, etc.

(3) The DC voltage at the device ball should never be above the MAX DC voltage to avoid impact on device reliability and lifetime POH (Power-On-Hours). The MAX DC voltage is defined as the highest allowed DC regulated voltage, without transients, seen at the ball.

In document AM571x Sitaraプロセッサシリコン・リビジョン2.0 datasheet (Rev. G) (Page 141-145)