7.3.1.1 1.8V and 3.3V Signal Transition Levels
7.5 Virtual and Manual I/O Timing Modes
Some of the timings described in the following sections require the use of Virtual or Manual I/O Timing Modes.
表7-2 provides a summary of the Virtual and Manual I/O Timing Modes across all device
interfaces. The individual interface timing sections found later in this document provide the full description of each applicable Virtual and Manual I/O Timing Mode. Refer to the "Pad Configuration" section of the TRM for the procedure on implementing the Virtual and Manual Timing Modes in a system.
表
表
7-2. Modes Summary
Virtual or Manual IO Mode Name Data Manual Timing Mode DPI Video Output
No Virtual or Manual IO Timing Mode Required DPI1/3 Video Output Default Timings - Rising-edge Clock Reference DSS_VIRTUAL1 DPI1/3 Video Output Default Timings - Falling-edge Clock Reference VOUT1_MANUAL1 DPI1 Video Output Alternate Timings
VOUT1_MANUAL4 DPI1 Video Output MANUAL4 Timings VOUT1_MANUAL5 DPI1 Video Output MANUAL5 Timings VOUT2_IOSET1_MANUAL1 DPI2 Video Output IOSET1 Alternate Timings
VOUT2_IOSET1_MANUAL2 DPI2 Video Output IOSET1 Default Timings - Rising-edge Clock Reference VOUT2_IOSET1_MANUAL3 DPI2 Video Output IOSET1 Default Timings - Falling-edge Clock Reference VOUT2_IOSET1_MANUAL4 DPI2 Video Output IOSET1 MANUAL4 Timings
VOUT2_IOSET1_MANUAL5 DPI2 Video Output IOSET1 MANUAL5 Timings VOUT2_IOSET2_MANUAL1 DPI2 Video Output IOSET2 Alternate Timings
VOUT2_IOSET2_MANUAL2 DPI2 Video Output IOSET2 Default Timings - Rising-edge Clock Reference
VOUT2_IOSET2_MANUAL3 DPI2 Video Output IOSET2 Default Timings - Falling-edge Clock Reference VOUT2_IOSET2_MANUAL4 DPI2 Video Output IOSET2 MANUAL4 Timings
VOUT2_IOSET2_MANUAL5 DPI2 Video Output IOSET2 MANUAL5 Timings VOUT3_MANUAL1 DPI3 Video Output Alternate Timings
VOUT3_MANUAL4 DPI3 Video Output MANUAL4 Timings VOUT3_MANUAL5 DPI3 Video Output MANUAL5 Timings GPMC
No Virtual or Manual IO Timing Mode Required GPMC Asynchronous Mode Timings and Synchronous Mode - Default Timings GPMC_VIRTUAL1 GPMC Synchronous Mode - Alternate Timings
McASP
No Virtual or Manual IO Timing Mode Required McASP1 Asynchronous and Synchronous Transmit Timings MCASP1_VIRTUAL1_SYNC_RX See表7-54
MCASP1_VIRTUAL2_ASYNC_RX See表7-54
No Virtual or Manual IO Timing Mode Required McASP2 Asynchronous and Synchronous Transmit Timings MCASP2_VIRTUAL1_SYNC_RX_80M See表7-55
MCASP2_VIRTUAL2_ASYNC_RX See表7-55 MCASP2_VIRTUAL3_SYNC_RX See表7-55 MCASP2_VIRTUAL4_ASYNC_RX_80M See表7-55
No Virtual or Manual IO Timing Mode Required McASP3 Synchronous Transmit Timings MCASP3_VIRTUAL2_SYNC_RX See表7-56
No Virtual or Manual IO Timing Mode Required McASP4 Synchronous Transmit Timings MCASP4_VIRTUAL1_SYNC_RX See表7-57
No Virtual or Manual IO Timing Mode Required McASP5 Synchronous Transmit Timings MCASP5_VIRTUAL1_SYNC_RX See表7-58
No Virtual or Manual IO Timing Mode Required McASP6 Synchronous Transmit Timings MCASP6_VIRTUAL1_SYNC_RX See表7-59
No Virtual or Manual IO Timing Mode Required McASP7 Synchronous Transmit Timings MCASP7_VIRTUAL2_SYNC_RX See表7-60
No Virtual or Manual IO Timing Mode Required McASP8 Synchronous Transmit Timings MCASP8_VIRTUAL1_SYNC_RX See表7-61
eMMC/SD/SDIO
No Virtual or Manual IO Timing Mode Required MMC1 DS (Pad Loopback), HS (Internal Loopback and Pad Loopback), SDR12 (Internal Loopback and Pad Loopback), and SDR25 Timings (Internal Loopback and Pad Loopback) Timings
MMC1_VIRTUAL1 MMC1 SDR50 (Pad Loopback) Timings MMC1_VIRTUAL4 MMC1 DS (Internal Loopback) Timings MMC1_VIRTUAL5 MMC1 SDR50 (Internal Loopback) Timings MMC1_VIRTUAL6 MMC1 DDR50 (Internal Loopback) Timings MMC1_MANUAL1 MMC1 DDR50 (Pad Loopback) Timings
MMC1_MANUAL2 MMC1 SDR104 Timings
No Virtual or Manual IO Timing Mode Required MMC2 Standard (Pad Loopback), High Speed (Pad Loopback) Timings MMC2_VIRTUAL2 MMC2 Standard (Internal Loopback), High Speed (Internal Loopback) Timings MMC2_MANUAL1 MMC2 DDR (Pad Loopback) Timings
MMC2_MANUAL2 MMC2 DDR (Internal Loopback) Timings
MMC2_MANUAL3 MMC2 HS200 Timings
No Virtual or Manual IO Timing Mode Required MMC3 DS, SDR12, HS, SDR25 Timings
MMC3_MANUAL1 MMC3 SDR50 Timings
No Virtual or Manual IO Timing Mode Required MMC4 DS, SDR12, HS, SDR25 Timings
QSPI
No Virtual or Manual IO Timing Mode Required QSPI Mode 3 Timings
QSPI1_MANUAL1 QSPI Mode 0 Timings
GMAC
No Virtual or Manual IO Timing Mode Required GMAC MII0/1 Timings
GMAC_RGMII0_MANUAL1 GMAC RGMII0 with Transmit Clock Internal Delay Enabled GMAC_RGMII1_MANUAL1 GMAC RGMII1 with Transmit Clock Internal Delay Enabled GMAC_RMII0_MANUAL1 GMAC RMII0 Timings
GMAC_RMII1_MANUAL1 GMAC RMII1 Timings VIP
VIP_MANUAL1 VIN1A (IOSET7) and VIN2A (IOSET10) Rise-Edge Capture Mode Timings VIP_MANUAL2 VIN1A (IOSET7) and VIN2A (IOSET10) Fall-Edge Capture Mode Timings VIP_MANUAL3 VIN2A (IOSET4/5/6) Rise-Edge Capture Mode Timings
VIP_MANUAL4 VIN2B (IOSET7/8/9) Rise-Edge Capture Mode Timings VIP_MANUAL5 VIN2A (IOSET4/5/6) Fall-Edge Capture Mode Timings VIP_MANUAL6 VIN2B (IOSET7/8/9) Fall-Edge Capture Mode Timings
VIP_MANUAL7 VIN1A (IOSET2/3/4) and VIN1B (IOSET4/7) and VIN2B (IOSET1) Rise-Edge Capture Mode Timings
VIP_MANUAL8 VIN1A (IOSET5/6) and VIN2A (IOSET7/8/9) Rise-Edge Capture Mode Timings VIP_MANUAL9 VIN1B (IOSET6/7) Rise-Edge Capture Mode Timings
VIP_MANUAL10 VIN1B (IOSET5) and VIN2B (IOSET2) Rise-Edge Capture Mode Timings VIP_MANUAL11 VIN1B (IOSET5) and VIN2B (IOSET2) Fall-Edge Capture Mode Timings
VIP_MANUAL12 VIN1A (IOSET2/3/4) and VIN1B (IOSET4/7) and VIN2B (IOSET1) Fall-Edge Capture Mode Timings
VIP_MANUAL13 VIN1A (IOSET5/6) and VIN2A (IOSET7/8/9) Fall-Edge Capture Mode Timings VIP_MANUAL14 VIN1B (IOSET6/7) Fall-Edge Capture Mode Timings
VIP_MANUAL15 VIN1A (IOSET8/9/10) Rise-Edge Capture Mode Timings VIP_MANUAL16 VIN1A (IOSET8/9/10) Fall-Edge Capture Mode Timings PRU-ICSS
No Virtual or Manual IO Timing Mode Required All PRU_ICSS Modes not covered below PR1_PRU1_DIR_IN_MANUAL PRU-ICSS1 PRU1 Direct Input Mode Timings PR1_PRU1_DIR_OUT_MANUAL PRU-ICSS1 PRU1 Direct Output Mode Timings PR1_PRU1_PAR_CAP_MANUAL PRU-ICSS1 PRU1 Parallel Capture Mode Timings PR2_PRU0_DIR_IN_MANUAL1 PRU-ICSS2 PRU0 IOSET1 Direct Input Mode Timings PR2_PRU0_DIR_IN_MANUAL2 PRU-ICSS2 PRU0 IOSET2 Direct Input Mode Timings PR2_PRU0_DIR_OUT_MANUAL1 PRU-ICSS2 PRU0 IOSET1 Direct Output Mode Timings PR2_PRU0_DIR_OUT_MANUAL2 PRU-ICSS2 PRU0 IOSET2 Direct Output Mode Timings PR2_PRU1_DIR_IN_MANUAL1 PRU-ICSS2 PRU1 IOSET1 Direct Input Mode Timings PR2_PRU1_DIR_IN_MANUAL2 PRU-ICSS2 PRU1 IOSET2 Direct Input Mode Timings PR2_PRU1_DIR_OUT_MANUAL1 PRU-ICSS2 PRU1 IOSET1 Direct Output Mode Timings PR2_PRU1_DIR_OUT_MANUAL2 PRU-ICSS2 PRU1 IOSET2 Direct Output Mode Timings PR2_PRU0_PAR_CAP_MANUAL1 PRU-ICSS2 PRU0 IOSET1 Parallel Capture Mode Timings PR2_PRU0_PAR_CAP_MANUAL2 PRU-ICSS2 PRU0 IOSET2 Parallel Capture Mode Timings PR2_PRU1_PAR_CAP_MANUAL1 PRU-ICSS2 PRU1 IOSET1 Parallel Capture Mode Timings PR2_PRU1_PAR_CAP_MANUAL2 PRU-ICSS2 PRU1 IOSET2 Parallel Capture Mode Timings
HDMI, EMIF, Timers, I2C, HDQ/1-Wire, UART, McSPI, USB, SATA, PCIe, DCAN, GPIO, KBD, PWM, ATL, JTAG, TPIU, RTC, SDMA, INTC, MLB
No Virtual or Manual IO Timing Mode Required All Modes
vinx_clki (positive-edge clocking)
V4 vinx_d[23:0]/sig
V5 vinx_clki
(negative-edge clocking)
SPRS906_TIMING_VIP_02
vinx_clki
V2
V1
V3
SPRS906_TIMING_VIP_01
表
7-3,
図7-4 and
図7-5 present timings and switching characteristics of the VIPs.
注 注意意
The I/O timings provided in this section are valid only for VIN1 and VIN2 if signals within a single IOSET are used. The IOSETs are defined in
表7-4 and
表7-5.
表
表
7-3. Timing Requirements for VIP
(3)(4)(5)NO. PARAMETER DESCRIPTION MIN MAX UNIT
V1 tc(CLK) Cycle time, vinx_clki(3) (5) 6.06(2) ns
V2 tw(CLKH) Pulse duration, vinx_clki high(3) (5) 0.45*P(2) ns
V3 tw(CLKL) Pulse duration, vinx_clki low(3) (5) 0.45*P(2) ns
V4 tsu(CTL/DATA-CLK) Input setup time, Control (vinx_dei, vinx_vsynci, vinx_fldi,
vinx_hsynci) and Data (vinx_dn) valid to vinx_clki transition(3) (4) (5) 3.11(2) ns V6 th(CLK-CTL/DATA) Input hold time, Control (vinx_dei, vinx_vsynci, vinx_fldi, vinx_hsynci)
and Data (vinx_dn) valid from vinx_clki transition(3) (4) (5) -0.05(2) ns (1) For maximum frequency of 165 MHz.
(2) P = vinx_clki period.
(3) x in vinx = 1a, 1b, 2a, 2b.
(4) n in dn = 0 to 7 when x = 1b, 2b.
n = 0 to 23 when x = 1a, 2a.
(5) i in clki, dei, vsynci, hsynci and fldi = 0 or 1.
図
図
7-4. Video Input Ports clock signal
図
図
7-5. Video Input Ports timings
SIGNALS IOSET2 IOSET3 IOSET4(1) IOSET5(1) IOSET6(1) IOSET7(1) IOSET8 IOSET9 IOSET10
BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX
vin1a
vin1a_clk0 P1 2 B11 4 B11 3 P4 4 P4 4 B26 8 AC5 9 E17 7 E17 7
vin1a_hsync0 N7 2 C11 4 C11 3 R3 4 P7 4 E21 8 AB8 9 F12 7 F12 7
vin1a_vsync0 R4 2 E11 4 E11 3 T2 4 N1 4 F20 8 AB5 9 G12 7 G12 7
vin1a_fld0 P9 2 D11 4 D11 3 P9 4 J7 4 F21 8 C17 9 C14 7 C14 7
vin1a_de0 N9 2 B10 4 B10 3 P7 5 H6 4 C23 8 AB4 9 D14 7 D14 7
vin1a_d0 M6 2 B7 4 B7 3 R6 4 R6 4 B14 8 AD6 9 D18 7 C17 7
vin1a_d1 M2 2 B8 4 B8 3 T9 4 T9 4 J14 8 AC8 9 B19 7 B19 7
vin1a_d2 L5 2 A7 4 A7 3 T6 4 T6 4 G13 8 AC3 9 F15 7 F15 7
vin1a_d3 M1 2 A8 4 A8 3 T7 4 T7 4 J11 8 AC9 9 B18 7 B18 7
vin1a_d4 L6 2 C9 4 C9 3 P6 4 P6 4 E12 8 AC6 9 A16 7 A16 7
vin1a_d5 L4 2 A9 4 A9 3 R9 4 R9 4 F13 8 AC7 9 C15 7 C15 7
vin1a_d6 L3 2 B9 4 B9 3 R5 4 R5 4 C12 8 AC4 9 A18 7 A18 7
vin1a_d7 L2 2 A10 4 A10 3 P5 4 P5 4 D12 8 AD4 9 A19 7 A19 7
vin1a_d8 L1 2 E8 4 E8 3 U2 4 U2 4 E15 8 AA4 9 F14 7 F14 7
vin1a_d9 K2 2 D9 4 D9 3 U1 4 U1 4 A20 8 AB3 9 G14 7 G14 7
vin1a_d10 J1 2 D7 4 D7 3 P3 4 P3 4 B15 8 AB9 9 A13 7 A13 7
vin1a_d11 J2 2 D8 4 D8 3 R2 4 R2 4 A15 8 AA3 9 E14 7 E14 7
vin1a_d12 H1 2 A5 4 A5 3 K7 4 K7 4 D15 8 D17 9 A12 7 A12 7
vin1a_d13 J3 2 C6 4 C6 3 M7 4 M7 4 B16 8 G16 9 B13 7 B13 7
vin1a_d14 H2 2 C8 4 C8 3 J5 4 J5 4 B17 8 A21 9 A11 7 A11 7
vin1a_d15 H3 2 C7 4 C7 3 K6 4 K6 4 A17 8 C18 9 B12 7 B12 7
vin1a_d16 R6 2 F11 4 F11 3 C18 8
vin1a_d17 T9 2 G10 4 G10 3 A21 8
vin1a_d18 T6 2 F10 4 F10 3 G16 8
vin1a_d19 T7 2 G11 4 G11 3 D17 8
vin1a_d20 P6 2 E9 4 E9 3 AA3 8
vin1a_d21 R9 2 F9 4 F9 3 AB9 8
vin1a_d22 R5 2 F8 4 F8 3 AB3 8
vin1a_d23 P5 2 E7 4 E7 3 AA4 8
vin1b
BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX
vin1b_clk1 P7 6 M4 4 V1 5 N9 6
vin1b_hsync1 H5 6 H5 6 U7 5 N7 6
vin1b_vsync1 H6 6 H6 6 V6 5 R4 6
vin1b_fld1 M4 6 W2 5 P4 6
vin1b_de1 N6 6 N6 6 V7 5 P9 6
vin1b_d0 K7 6 K7 6 U4 5 R6 6
vin1b_d1 M7 6 M7 6 V2 5 T9 6
vin1b_d2 J5 6 J5 6 Y1 5 T6 6
vin1b_d3 K6 6 K6 6 W9 5 T7 6
vin1b_d4 J7 6 J7 6 V9 5 P6 6
vin1b_d5 J4 6 J4 6 U5 5 R9 6
vin1b_d6 J6 6 J6 6 V5 5 R5 6
vin1b_d7 H4 6 H4 6 V4 5 P5 6
(1) The IOSET under this column is only applicable for pins with alternate functionality which allows either VIN1 or VIN2 signals to be mapped to the pins. These alternate functions are controlled via CTRL_CORE_VIP_MUX_SELECT register. For more information on how to use these options, please refer to Device TRM, chapter Control Module, section Pad Configuration Registers.
表表
7-5. VIN2 IOSETs
SIGNALS IOSET1 IOSET2 IOSET4 IOSET5 IOSET6 IOSET7(1) IOSET8(1) IOSET9(1) IOSET10(1)
BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX BALL MUX
vin2a
vin2a_clk0 E1 0 E1 0 V1 4 B11 3 P4 4 P4 4 B26 8
vin2a_hsync0 G1 0 G1 0 U7 4 C11 3 R3 4 P7 4 E21 8
vin2a_vsync0 G6 0 G6 0 V6 4 E11 3 T2 4 N1 4 F20 8
vin2a_fld0 H7 0 G2 1 W2 4 D11 3 P9 4 J7 4 F21 8
vin2a_de0 G2 0 V7 4 B10 3 P7 5 H6 4 C23 8
vin2a_d0 F2 0 F2 0 U4 4 B7 3 R6 4 R6 4 B14 8
vin2a_d1 F3 0 F3 0 V2 4 B8 3 T9 4 T9 4 J14 8
vin2a_d2 D1 0 D1 0 Y1 4 A7 3 T6 4 T6 4 G13 8
vin2a_d3 E2 0 E2 0 W9 4 A8 3 T7 4 T7 4 J11 8
vin2a_d4 D2 0 D2 0 V9 4 C9 3 P6 4 P6 4 E12 8
vin2a_d5 F4 0 F4 0 U5 4 A9 3 R9 4 R9 4 F13 8
vin2a_d6 C1 0 C1 0 V5 4 B9 3 R5 4 R5 4 C12 8