注: The OSC_32K_CLK clock, provided by the On-die 32K RC oscillator, inside of the SoC, is not accurate 32kHz clock.
The frequency may significantly vary with temperature and silicon characteristics.
For more information about OSC_32K_CLK see the Device TRM, Chapter: Power, Reset, and Clock Management.
6.2 DPLLs, DLLs Specifications
注注: For more information, see:
• Power, Reset, and Clock Management / Clock Management Functional / Internal Clock Sources / Generators / Generic DPLL Overview Section
and
• Display Subsystem / Display Subsystem Overview section of the Device TRM.
To generate high-frequency clocks, the device supports multiple on-chip DPLLs controlled directly by the PRCM module. They are of two types: type A and type B DPLLs.
• They have their own independent power domain (each one embeds its own switch and can be controlled as an independent functional power domain)
• They are fed with ALWAYS ON system clock, with independent control per DPLL.
The different DPLLs managed by the PRCM are listed below:
• DPLL_MPU: It supplies the MPU subsystem clocking internally.
• DPLL_IVA: It feeds the IVA subsystem clocking.
• DPLL_CORE: It supplies all interface clocks and also few module functional clocks.
• DPLL_PER: It supplies several clock sources: a 192-MHz clock for the display functional clock, a 96-MHz functional clock to subsystems and peripherals.
• DPLL_ABE: It provides clocks to various modules within the device.
• DPLL_USB: It provides 960M clock for USB modules (USB1/2/3/4).
• DPLL_GMAC: It supplies several clocks for the Gigabit Ethernet Switch (GMAC_SW).
• DPLL_DSP: It feeds the DSP Subsystem clocking.
• DPLL_GPU: It supplies clock for the GPU Subsystem.
• DPLL_DDR: It generates clocks for the two External Memory Interface (EMIF) controllers and their
associated EMIF PHYs.
controllers.
注
注: The following DPLLs are controlled by the clock manager located in the always-on Core power domain (CM_CORE_AON):
• DPLL_MPU, DPLL_IVA, DPLL_CORE, DPLL_ABE, DPLL_DDR, DPLL_GMAC,
DPLL_PCIE_REF, DPLL_PER, DPLL_USB, DPLL_DSP, DPLL_GPU, APLL_PCIE_REF.
For more information on CM_CORE_AON and CM_CORE or PRCM DPLLs, see the Power, Reset, and Clock Management (PRCM) chapter of the Device TRM.
The following DPLLs are not managed by the PRCM:
• DPLL_VIDEO1; (It is controlled from DSS)
• DPLL_HDMI; (It is controlled from DSS)
• DPLL_SATA; (It is controlled from SATA)
• DPLL_DEBUG; (It is controlled from DEBUGSS)
• DPLL_USB_OTG_SS; (It is controlled from OCP2SCP1)
注
注: For more information for not controlled from PRCM DPLL’s see the related chapters in TRM.
6.2.1 DPLL Characteristics
The DPLL has three relevant input clocks. One of them is the reference clock (CLKINP) used to generated the synthesized clock but can also be used as the bypass clock whenever the DPLL enters a bypass mode. It is therefore mandatory. The second one is a fast bypass clock (CLKINPULOW) used when selected as the bypass clock and is optional. The third clock (CLKINPHIF) is explained in the next paragraph.
The DPLL has three output clocks (namely CLKOUT, CLKOUTX2, and CLKOUTHIF). CLKOUT and CLKOUTX2 run at the bypass frequency whenever the DPLL enters a bypass mode. Both of them are generated from the lock frequency divided by a post-divider (namely M2 post-divider). The third clock, CLKOUTHIF, has no automatic bypass capability. It is an output of a post-divider (M3 post-divider) with the input clock selectable between the internal lock clock (Fdpll) and CLKINPHIF input of the PLL through an asynchronous multplexing.
For more information, see the Power Reset Controller Management chapter of the Device TRM.
表
6-12 summarizes DPLL type described in 6.2, DPLLs, DLLs Specifications introduction.
表
表
6-12. DPLL Control Type
DPLL NAME TYPE CONTROLLED BY PRCM
DPLL_ABE 表6-13(Type A) Yes(1)
DPLL_CORE 表6-13(Type A) Yes(1)
DPLL_DEBUGSS 表6-13(Type A) No(2)
DPLL_DSP 表6-13(Type A) Yes(1)
DPLL_GMAC 表6-13(Type A) Yes(1)
DPLL_HDMI 表6-14(Type B) No(2)
DPLL_IVA 表6-13(Type A) Yes(1)
DPLL_MPU 表6-13(Type A) Yes(1)
DPLL_PER 表6-13(Type A) Yes(1)
APLL_PCIE 表6-13(Type A) Yes
DPLL_PCIE_REF 表6-14(Type B) Yes(1)
DPLL_SATA 表6-14(Type B) No(2)
DPLL_USB 表6-14(Type B) Yes(1)
DPLL_USB_OTG_SS 表6-14(Type B) No(2)
DPLL_VIDEO1 表6-13(Type A) No(2)
DPLL_DDR 表6-13(Type A) Yes(1)
DPLL_GPU 表6-13(Type A) Yes(1)
(1) DPLL is in the always-on domain.
(2) DPLL is not controlled by the PRCM.
表
6-13 and
表6-14 summarize the DPLL characteristics and assume testing over recommended operating conditions.
表表
6-13. DPLL Type A Characteristics
NAME DESCRIPTION MIN TYP MAX UNIT COMMENTS
finput CLKINP input frequency 0.032 52 MHz FINP
finternal Internal reference frequency 0.15 52 MHz REFCLK
fCLKINPHIF CLKINPHIF input frequency 10 1400 MHz FINPHIF
fCLKINPULOW CLKINPULOW input frequency 0.001 600 MHz
Bypass mode: fCLKOUT= fCLKINPULOW/ (M1 + 1) if ulowclken = 1(6)
fCLKOUT CLKOUT output frequency 20(1) 1800(2) MHz [M / (N + 1)] × FINP× [1 / M2]
(in locked condition)
fCLKOUTx2 CLKOUTx2 output frequency 40(1) 2200(2) MHz 2 × [M / (N + 1)] × FINP× [1 /
M2] (in locked condition) fCLKOUTHIF CLKOUTHIF output frequency
20(3) 1400(4) MHz FINPHIF/ M3 if clkinphifsel = 1
40(3) 2200(4) MHz 2 × [M / (N + 1)] × FINP× [1 / M3] if clkinphifsel = 0 fCLKDCOLDO DCOCLKLDO output
frequency 40 2800 MHz 2 × [M / (N + 1)] × FINP(in
locked condition)
tlock Frequency lock time 6 + 350 ×
REFCLK µs
plock Phase lock time 6 + 500 ×
REFCLK µs
trelock-L
Relock time—Frequency lock(5)(LP relock time from bypass)
6 + 70 ×
REFCLK µs DPLL in LP relock time:
lowcurrstdby = 1 prelock-L Relock time—Phase lock(5)
(LP relock time from bypass)
6 + 120 ×
REFCLK µs DPLL in LP relock time:
lowcurrstdby = 1 trelock-F
Relock time—Frequency lock(5)(fast relock time from bypass)
3.55 + 70 ×
REFCLK µs DPLL in fast relock time:
lowcurrstdby = 0 prelock-F Relock time—Phase lock(5)
(fast relock time from bypass)
3.55 + 120 ×
REFCLK µs DPLL in fast relock time:
lowcurrstdby = 0 (1) The minimum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1.
For M2 > 1, the minimum frequency on these clocks will further scale down by factor of M2.
(2) The maximum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1.
(3) The minimum frequency on CLKOUTHIF is assuming M3 = 1. For M3 > 1, the minimum frequency on this clock will further scale down by factor of M3.
(4) The maximum frequency on CLKOUTHIF is assuming M3 = 1.
(5) Relock time assumes typical operating conditions, 10°C maximum temperature drift.
NAME DESCRIPTION MIN TYP MAX UNIT COMMENTS
finput CLKINP input clock frequency 0.62 60 MHz FINP
finternal REFCLK internal reference
clock frequency 0.62 2.5 MHz [1 / (N + 1)] × FINP
fCLKINPULOW CLKINPULOW bypass input
clock frequency 0.001 600 MHz
Bypass mode: fCLKOUT= fCLKINPULOW/ (M1 + 1) If ulowclken = 1(4) fCLKLDOOUT CLKOUTLDO output clock
frequency 20(1)(5) 2500(2)(5) MHz M / (N + 1)] × FINP× [1 / M2]
(in locked condition) fCLKOUT CLKOUT output clock
frequency 20(1)(5) 1450(2)(5) MHz [M / (N + 1)] × FINP× [1 / M2]
(in locked condition) fCLKDCOLDO Internal oscillator (DCO) output
clock frequency
750(5) 1500(5) MHz [M / (N + 1)] × FINP(in locked condition)
1250(5) 2500(5) MHz
tJ
CLKOUTLDO period jitter
–2.5% 2.5% The period jitter at the output
clocks is ± 2.5% peak to peak CLKOUT period jitter
CLKDCOLDO period jitter
tlock Frequency lock time 350 ×
REFCLKs µs
plock Phase lock time 500 ×
REFCLKs µs
trelock-L Relock time—Frequency lock(3) (LP relock time from bypass)
9 + 30 ×
REFCLKs µs
prelock-L Relock time—Phase lock(3)(LP relock time from bypass)
9 + 125 ×
REFCLKs µs
(1) The minimum frequency on CLKOUT is assuming M2 = 1.
For M2 > 1, the minimum frequency on this clock will further scale down by factor of M2.
(2) The maximum frequency on CLKOUT is assuming M2 = 1.
(3) Relock time assumes typical operating conditions, 10°C maximum temperature drift.
(4) Bypass mode: fCLKOUT= FINPif ULOWCLKEN = 0. For more information, see the Device TRM.
(5) For output clocks, there are two frequency ranges according to the SELFREQDCO setting. For more information, see the Device TRM.
6.2.2 DLL Characteristics
表
6-15 summarizes the DLL characteristics and assumes testing over recommended operating conditions.
表
表
6-15. DLL Characteristics
NAME DESCRIPTION MIN TYP MAX UNIT
finput Input clock frequency (EMIF_DLL_FCLK) 266 MHz
tlock Lock time 50k cycles
trelock Relock time (a change of the DLL frequency implies that DLL must relock) 50k cycles