Package Thermal Characteristics

In document AM571x Sitaraプロセッサシリコン・リビジョン2.0 datasheet (Rev. G) (Page 173-180)

5.8 Thermal Characteristics

5.8.1 Package Thermal Characteristics

5-21 provides the thermal resistance characteristics for the package used on this device.

注: Power dissipation of 1.5 W and an ambient temperature of 85ºC is assumed for ABC package.

表表

5-21. Thermal Resistance Characteristics

NO. PARAMETER DESCRIPTION °C/W(1) AIR FLOW (m/s)(2)

T1 RΘJC Junction-to-case 0.41 N/A

T2 RΘJB Junction-to-board 4.74 N/A

T3

JA

Junction-to-free air 11.9 0

T4

Junction-to-moving air

8.9 1

T5 8.0 2

T6 7.4 3

T7

ΨJT Junction-to-package top

0.22 0

T8 0.22 1

T9 0.22 2

T10 0.23 3

T11

ΨJB Junction-to-board

4.12 0

T12 3.73 1

T13 3.59 2

T14 3.48 3

(1) These measurements were conducted in a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] measurement, which was conducted in a JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards:

– JESD51-2,Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air) – JESD51-3,Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

– JESD51-7,High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages – JESD51-9,Test Boards for Area Array Surface Mount Packages

(2) m/s = meters per second

operation. The power supply names described in this section comprise a superset of a family of

compatible devices. Some members of this family will not include a subset of these power supplies and their associated device modules. Refer to the 4.2, Ball Characteristics of the 4, Terminal Configuration and Functions to determine which power supplies are applicable.

注: RTC only mode is not supported feature.

Note 12 Note 13

Note 14 Note 9

Note 6

Note 7 vdds18v, vdds_mlbp, vdds18v_ddr1, vdda_rtc(3)

vdda_per, vdda_ddr, vdda_debug, vdda_dsp_iva, vdda_core_gmac, vdda_gpu, vdda_video, vdda_mpu, vdda_osc

vdds_ddr1, ddr1_vref0(16)

vdd, vdd_rtc(3)

VD_CORE BOOT voltage

VD_MPU BOOT voltage

VD_IVA BOOT voltage

VD_GPU BOOT voltage

VD_DSP BOOT voltage vdd_mpu

vdd_iva

vdd_gpu

vdd_dsp vdda_usb1, vdda_usb2, vdda_hdmi, vdda_pcie, vdda_pcie0, vdda_sata, vdda_usb3, vdda_csi vddshv1, vddshv2, vddshv3, vddshv4, vddshv5 , vddshv6, vddshv7, vddshv9, vddshv10, vddshv11

(3)

vdda33v_usb1, vdda33v_usb2

vddshv8

xi_osc0

rtc_porz

porz

sysboot[15:0]

rstoutn

SPRS906_ELCH_04

Valid Config

Note 11

5-2. Power-Up Sequencing

(1) Grey shaded areas are windows where it is valid to ramp the voltage rail.

(2) Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.

(3) RTC-only mode is not used and the following combinations are approved:

If combinations listed above are not followed then sequencing for these 3 voltage rails should follow the RTC mode timing requirements.

When using RTC mode timing:

- vdda_rtc rises coincident with, or before, the 1.8V interface supplies (such as vdds18v).

- vdd_rtc rises coincident with vdd, or it may rise earlier. If rising earlier, it must rise after the 1.8V interface supplies.

- vddshv5 rises coincident with the other vddshvn rails (of the same voltage) or it can rise about the same time as the 1.8V PHY supplies (such as vdd_usb1).

(4) vdd must ramp before or at the same time as vdd_mpu, vdd_gpu, vdd_dsp and vdd_iva.

(5) vdd_mpu, vdd_gpu, vdd_dsp, vdd_iva can be ramped at the same time or can be staggered.

(6) If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.

(7) vddshv8 is separated out to show support for dual voltage. If single voltage is used then vddshv8 can be combined with other vddshvn rails but vddshv8 must ramp after vdd.

(8) vdds and vdda rails must not be combined together, with the one exception of vdda_rtc when RTC-mode is not supported.

(9) Pulse duration: rtc_porz must remain low 1ms after vdda_rtc, vddshv5, and vdd_rtc are ramped and stable.

(10) The SYS_32K source must be stable and at a valid frequency 1ms prior to de-asserting rtc_porz high.

(11) Pulse duration: porz must remain low a minimum of 12P(15)after xi_osc0 is stable and at a valid frequency. porz must also remain low until all supply rails are valid and stable. resetn must be high prior to, or simultaneous with, porz rising. During initial power-up, resetn can rise any time after, or concurrently with, its supply voltage, vddshv3 rising.

(12) Setup time: sysboot[15:0] pins must be valid 2P(15)before porz is de-asserted high.

(13) Hold time: sysboot[15:0] pins must be valid 15P(15)after porz is de-asserted high.

(14) porz to rstoutn delay is 2ms.

(15) P = 1/(SYS_CLK1/610) frequency in ns.

(16) ddr1_vref0 may rise coincident with vdds_ddr1 or at a later time. However, it must be valid before porz rising.

vdda_per, vdda_ddr, vdda_debug,

vdda_dsp_iva, ,

vdda_gpu, vdda_video, vdda_mpu, vdda_osc vdda_core_gmac vdda_usb1, vdda_usb2, vdda_hdmi,

vdda_pcie, vdda_pcie0, vdda_sata, vdda_usb3, vdda_csi

vdds_ddr1, ddr1_vref0(11) vdd, vdd_rtc(4) vdd_mpu vdd_gpu vdd_dsp

vdd_iva vddshv8

vdda33v_usb1, vdda33v_usb2

xi_osc0

SPRS906_ELCH_05

Note 8

Note 7

vdds18v, vdds_mlbp, vdds18v_ddr1, vdda_rtc(4)

Note 9

5-3. Power-Down Sequencing

(10)(12)

(1) Grey shaded areas are windows where it is valid to ramp the voltage rail.

(2) Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.

(3) xi_osc0 can be turned off anytime after porz assertion and must be turned off before vdda_osc voltage rail is shutdown.

(4) RTC-only mode is not used and the following combinations are approved:

- vdda_rtc can be combined with vdds18v - vdd_rtc can be combined with vdd

- vddshv5 can be combined with other 1.8V or 3.3V vddshvn rails

If combinations listed above are not followed then sequencing for these 3 voltage rails should follow the RTC mode timing requirements.

When using RTC mode timing:

- vdda_rtc falls coincident with, or later than, the 1.8V interface supplies (such as vdds18v).

- vdd_rtc falls coincident with vdd, or it may fall later. If falling later, it must fall before, or coincident with, the 1.8V interface supplies.

- vddshv5 falls coincident with the other vddshvn rails (of the same voltage) or it can fall about the same time as the 1.8V PHY supplies (such as vdd_usb1).

vddshv1, vddshv2, vddshv3, vddshv4, vddshv6, vddshv7, vddshv9, vddshv10, vddshv11, vddshv8(Note 2)

vdds18v

Vdelta (Note1)

SPRS85v_ELCH_06

- vddshv[1-7,9-11] is allowed to ramp down at either of the two points shown in the timing diagram in either 1.8V mode or in 3.3V mode.

- If vddshv[1-7,9-11] ramps down at the later time in the diagram then the board design must guarantee that the vddshv[1-7,9-11] rail is never higher than 2.0 V above the vdds18v rail.

(8) vddshv8 is separated out to show support for dual voltage. If a dedicated LDO/supply source is used for vddshv8, then vddshv8 ramp down should occur at one of the two earliest points in the timing diagram. If vddshv8 is powered by the same supply source as the other vddshv[1-7,9-11] rails, then it is allowed to ramp down at either of the last two points in the timing diagram.

(9) The 1.8V vdda_* supplies can either ramp down at the earlier time period shown or can be delayed to ramp down after the core supplies coincident with the vdds18v supply as long as porz is asserted (low) during the power down sequence.

(10) The power down sequence shown is the most general case and is always valid. An accelerated power down sequence is also available but is only valid when porz is asserted (low). This accelerated power down sequence has been implemented in the companion PMIC that is recommended for use with this SOC. The accelerated sequence has porz go low first, then all 3.3V supplies simultaneously second, core supplies, DDR supplies and DDR references simultaneously third and all 1.8V supplies simultaneously last.

(11) ddr1_vref0 may fall coincident with vdds_ddr1, or at a prior time but after porz is asserted low.

(12) Ramped Down is defined as reaching a voltage level of no more than 0.6V.

5-4 describes vddshv[1-7,9-11] Supplies Falling Before vdds18v Supplies Delta.

5-4. vddshv* Supplies Falling After vdds18v Supplies Delta

(1) Vdelta MAX = 2V

(2) If vddshv8 is powered by the same supply source as the other vddshv[1-7,9-11] rails.

注: For more information, see Power, Reset, and Clock Management / PRCM Environment / External Clock Signal and Power Reset / PRCM Functional Description / PRCM Clock Manager Functional Description section of the Device TRM.

注: Audio Back End (ABE) module is not supported for this family of devices, but “ABE”

name is still present in some clock or DPLL names.

The device operation requires the following clocks:

• The 32 kHz frequency is used for low frequency operation. It supplies the wake-up domain for

operation in lowest power mode. This is an optional clock and will be supplied by on chip divider + mux (FUNC_32K_CLK) incase it is not available on external pin.

• The system clocks, SYS_CLKIN1(Mandatory) and SYS_CLKIN2(Optional) are the main clock sources of the device. They supply the reference clock to the DPLLs as well as functional clock to several modules.

The Device also embeds an internal free-running 32-kHz oscillator that is always active as long as the the wake-up (WKUP) domain is supplied.

6-1 shows the external input clock sources and the output clocks to peripherals.

clkout1

To quartz (from oscillator output).

resetn rstoutn

External Reference Clock [3:0].

For Audio and other Peripherals xref_clk1

sysboot[15:0]

From quartz (19.2, 20 or 27 MHz)

or from CMOS square clock source (19.2, 20 or 27MHz).

Boot Mode Configuration xi_osc1

Warm reset output.

Device reset input.

porz Power ON Reset.

xi_osc0 xo_osc0

xo_osc1

From quartz (range from MHz)

or from CMOS square clock source(range from MHz).

19.2 to 32

12 to 38.4

To quartz (from oscillator output).

clkout2

clkout3

xref_clk0

xref_clk2

xref_clk3

Output clkout[3:1] clocks come from:

• Either the input system clock and alternate clock (xi_osc0 or xi_osc1)

• Or a CORE clock (from CORE output)

• Or a 192-MHz clock (from PER DPLL output).

To quartz (from oscillator output).

rtc_osc_xo

6-1. Clock Interface

6.1 Input Clock Specifications

In document AM571x Sitaraプロセッサシリコン・リビジョン2.0 datasheet (Rev. G) (Page 173-180)