3.2 ᬌ⸛ᢥ₂
3.2.5 䉲䊮䉫䊦䉟䊔䊮䊃⽎䈮࿃䈜䉎䊂䊷䉺䉣䊤䊷䈱䊉䊷䊙䊥䊷䉥䊐䊃䊤䊮䉳䉴䉺䉕䈚䈢વ
ᢥ₂ฬ Single Event-Induced Error Propagation Through Nominally-off Transmission Gates
ౖ IEEE Transaction on Nuclear Science, Vol.53, No. 6, pp.3558- 3562 , Dec. 2006.
⪺⠪ฬ J. M. Hutson, V. Ramachandran, B. L. Bhuva, X. Zhu ,R. D. Schrimpf, Amusan, L. M. Massengill
ኻ⽎䊂䊋䉟䉴 ඨዉ䊨䉳䉾䉪࿁〝
ታ㛎⸳ 䋭
ᾖ✢⒳䈶 䉣䊈䊦䉩䊷䈱ಽ
㊀䉟䉥䊮 න⊒⽎䈲
Ⓧ▚✢㊂ലᨐ䈱ಽ
න⊒ォ⽎
ታ㛎䈲ℂ⺰䈱ಽ ℂ⺰
(1) ⷐ㩷
SET(Single Event Transient)䈮䉋䉎65nmઍ䈪䈱D-䊐䊥䉾䊒䊐䊨䉾䊒࿁〝䈪䈱⺋䊤䉾䉼⽎
䈏䇮䊉䊷䊙䊥䊷䉥䊐䈱䊃䊤䊮䉴䊚䉾䉲䊢䊮䉭䊷䊃䉕䊃䊤䊮䉳䉢䊮䊃䊌䊦䉴䈏વ䈜䉎䈖䈫䈪↢䈛䉎䈖䈫䈏䉌 䈎䈮䈭䈦䈢䇯䈖䈱⽎䈲䉟䉥䊮ᾖ䉕ฃ䈔䈢 䊉䊷䊄䈱㔚䈏䇮㔚Ḯ䊧䊔䊦䉋䉍䉅⽶䈮ᝄ䉍ㄟ䉃䈖䈫 䈮䉋䉍↢䈛䉎䇯ᧄ⽎䈲䇮⚛ሶ䈱ᓸ⚦ൻ䈮䉋䉍䇮䊉䊷䊄ኈ㊂䈏ዊ䈘䈒䈭䉎䈫㗼ൻ䈚䇮࿁〝䉲䊚䊠䊧䊷 䉲䊢䊮䈮䉋䉍䇮䉪䊨䉾䉪ᦼ䈱4ಽ䈱1䈮⋧ᒰ䈜䉎ᤨ㑆䇮SET䈮䉋䉎䉣䊤䊷䈱䊥䉴䉪䈏Ⴧᄢ䈜䉎䈖䈫䈏䉒 䈎䈦䈢䇯
(2) ᐨ⺰㩷
✢࿃䈱䉸䊐䊃䉣䊤䊷䈲䉰䊑䊙䉟䉪䊨䊮 CMOS䈮䈍䈇䈩䈲䇮㔚Ḯ㔚䈱ૐਅ䇮䊉䊷䊄ኈ㊂䈱 ૐਅ䈱ᓇ㗀䈪䇮ା㗬ᕈ㗴䈫䈚䈩㗼ൻ䈚䈩䈇䉎䇯৻⥸⊛䈮䇮CMOS⚵䉂ว䉒䈞⺰ℂ࿁〝䈪䈱 SET䈮䉋䉎⺋േ䈲䇮⺋䊌䊦䉴䈏䊤䉾䉼䊉䊷䊄䈮ᦠ䈐ㄟ䉁䉏䉎䈖䈫䈪↢䈛䉎䈱䈪䇮ㅢᏱ䈲䇮䉪䊨䉾䉪䈏 ৼᐲㆫ⒖䈜䉎䉺䉟䊚䊮䉫䈮䇮SET䈮䉋䉎⺋䊌䊦䉴䈏વ䈜䉎႐ว䈮㒢䉍䇮⺋ᦠ䈐ㄟ䉂䈏䈍䈐䉎䇯䈚䈎䈚 䈭䈏䉌䇮ᓸ⚦ൻ䈮䈇䇮േᵄᢙ䈏ᢙGHz䉁䈪Ⴧട䈚䈩䈒䉎䈫䇮ᢙ䉪䊨䉾䉪䉰䉟䉪䊦೨䈱䇮䉟䉥䊮
䉇䇮ᓥ᧪䈲䇮ή㑐ଥ䈱䊉䊷䊄䈎䉌䈱ᓇ㗀䈪SET䈏↢䈛䉎䈖䈫䈏䈅䉎䇯䈖䈱䉋䈉䈭ᣂ⽎䈏䈐䉎䈫䇮
ᤨ㑆䊄䊜䉟䊮䈪䈱䊥䉻䊮䉻䊮䉲䊷䈭䈬䈱ᚻᴺ䈏䈋䈭䈒䈭䉎น⢻ᕈ䈏䈅䉎䇯䈖䈱ᣂ⽎䈲䇮䊂䊋䉟䉴䉰 䉟䉵䈏ዊ䈘䈒䈭䉍䇮േ㔚ᵹ䈏ዊ䈘䈒䈭䉍䇮േᵄᢙ䈏Ⴧട䈜䉎䈫㗼ൻ䈜䉎䈫੍ᗐ䈘䉏䉎䈢䉄䇮䈠 䈱ਇ⦟䊜䉦䊆䉵䊛䉕ℂ⸃䈜䉎䈖䈫䈲䈐䉒䉄䈩㊀ⷐ䈪䈅䉎䇯ᧄ⎇ⓥ䈪䈲䇮䉲䊚䊠䊧䊷䉲䊢䊮䈮䉋䉍䊂䊋䉟䉴 䊧䊔䊦䇮࿁〝䊧䊔䊦䈮䈍䈇䈩䇮⚵䉂ว䉒䈞䊨䉳䉾䉪࿁〝䈪䈱SET⽎䈮䈧䈇䈩⸃ᨆ䉕ട䈋䈢䇯
(3) Technology and Simulation setup㩷
65nm䈫130nm䈱CMOSᛛⴚઍ䈮䈧䈇䈩䉲䊚䊠䊧䊷䉲䊢䊮䊔䊷䉴䈪䈱ᬌ⸛䉕ታᣉ䈚䈢䇯130nm
ઍ䈱CMOSᛛⴚ䈮ኻ䈚䈩䈲䇮3ᰴర䈱TCAD䋨䊂䊋䉟䉴䉲䊚䊠䊧䊷䉲䊢䊮䋩䈫Mixed mode 䉲䊚䊠 䊧䊷䉲䊢䊮䉕ታᣉ䈚䇮䊂䊋䉟䉴䊧䊔䊦䈪䈱SET⽎䈱⸃ᨆ䉕ታᣉ䈚䈢䇯65nmઍ䈪䈱SET⸃ᨆ䈮 䈲䇮TCAD䈱⚿ᨐ䈮䉅䈫䈨䈇䈢MOSFET䉮䊮䊌䉪䊃䊝䊂䊦䉕ᚑ䈚HSPICE䈪䈱࿁〝⸃ᨆ䉕ታ ᣉ䈚䈢䇯࿁〝䉲䊚䊠䊧䊷䉲䊢䊮ᬌ⸛ᤨ䈱䉪䊨䉾䉪ᵄᢙ䈲․䈮䇮␜䈘䈭䈇㒢䉍2GHz䈪䈅䉎䇯
(4) Error Mechanisms㩷
ㆊઍ䈮䈍䈇䈩䈲䇮䉟䉥䊮䈮䉋䉎
㓸㔚⩄㊂䈫䊉䊷䊄㔚⩄㊂䈲䇮ห⒟ᐲ䈪䈅䉍䇮 SET䊌䊦䉴䈲䇮㓸㔚⩄㊂䈮Ყ䈚䇮䊂䊋 䉟 䉴 䈱 㚟 േ 㔚 ᵹ 䈮 Ყ 䈚 䈩 䈇 䈢 䇯 ࿑ 3.2.5-1䈮 䊉 䊷 䊄 䈮 䉟 䉥 䊮 䈏 ᾖ 䈚 䈢 㓙 䈱 䇮 CMOS Inverter࿁〝䈱╬ଔ࿁〝䉕␜䈜䈏䇮 䊉䊷䊄㔚䈮ᓇ㗀䉕ਈ䈋䉎䈱䈲䇮䉟䉥䊮䈮 䉋 䉎 ⺃ 㔚 ᵹ 䇮PMOS䈱 㘻 㔚 ᵹ 䇮 Capacitor䈱ల㔚ᵹ䈪䈅䉎䇯Deep 䉰䊑䊚䉪 䊨䊮ઍ䈮䈍䈇䈩䈲䇮䊃䊤䊮䉳䉴䉺䈱㚟േ㔚ᵹ 䈲ᢙ⊖㱘A䈮ኻ䈚䇮䉟䉥䊮䈮䉋䉎㔚ᵹ䈲䇮
ᢙmA.䈫ᄢ䈐䈇䈱䈪䇮䉟䉥䊮㔚ᵹ䈏䇮䊉䊷䊄䈱ㆊᷰᔕ╵䉕ᓞೣ䈜䉎䇯䈠䈱ὑ䇮䉟䉥䊮㔚ᵹ䈱ᓇ㗀䈪䇮 䊉䊷䊄㔚䈲䇮ƦV=ƦQ/C䈱㑐ଥ䈮ၮ䈨䈐䇮㔚Ḯ䊧䊔䊦䉕䈋䈩䇮ᄌേ䈚䇮ᢔጀ䈱ነ↢䉻䉟䉥䊷䊄 䉕Forward䈮䊋䉟䉝䉴䈚䇮䈠䈱䉺䊷䊮䉥䊮㔚䉕
ട 䈋 䈢 㔚 䈮 䉁 䈪 ᄌ ൻ 䈜 䉎 䇯 ࿑ 3.2.5-2䈮 䇮 TCAD䉲䊚䊠䊧䊷䉲䊢䊮(130nmઍ䋩䈮䉋䉎SET
⸃ᨆ⚿ᨐ䋨䉟䊮䊋䊷䉺䊷䈱䊉䊷䊄㔚䈱ᤨ㑆ᔕ
╵ᵄᒻ䋩䉕␜䈜䇯ὐ✢䈲䉟䊮䊋䊷䉺䉕᭴ᚑ䈜䉎 pMOSFET䈱㚟േ㔚ᵹ䈮⋧ᒰ䈚䇮䉟䉥䊮⺃㔚 ᵹ䈏䈖䈱㔚ᵹ䉋䉍ዊ䈘䈒䈭䉌䈭䈇㒢䉍䇮䊉䊷䊄㔚
䈲㔚Ḯ䊧䊔䊦䉕䈋䈩ᄌേ䈜䉎䇯䉁䈢䇮䊉䊷䊄㔚
䈲䇮ᢔ㔚ᵹ䈮䉋䉍䉁䈦䈩䈇䉎䈖䈫䈏್䈚 䈢䇯SET䈱䊌䊦䉴䈲ᓸ⚦ൻ䈫䈮ᢔ㔚ᵹ䈪 ᓞೣ䈘䉏䉎䈏䇮䈖䉏䈲䇮䊃䊤䊮䉳䉴䉺䈱䉼䊞䊈䊦
䈏ዊ䈘䈒䈭䉍䇮㚟േ㔚ᵹ䈏ዊ䈘䈇䈖䈫䈏ේ࿃䈪䈅 䉎䇯
࿑ 3.2.5-1 ౝ䈜䉎䉻䉟䉥䊷䊄䉕䉃ౖဳ⊛䈭 䉟䊮䊋䊷䉺䇯⍫ශ䈲䉟䉥䊮䉕␜䈜䇯
࿑ 3.2.5-2 SET 䈮䉋䉎⺃㔚ᵹ䈫 䊉䊷䊄㔚䇯
(5) D-䊐䊥䉾䊒䊐䊨䉾䊒䈪䈱Upset㩷
࿑ 3.2.5-3䈮䇮D-䊐䊥䉾䊒䊐䊨䉾䊒࿁〝䉕␜䈜䇯ㅢᏱ䇮䊐䊥䉾䊒䊐䊨䉾䊒࿁〝䈱ੑ䈧䈱䊤䉾䉼࿁〝䈲
䊃䊤䊮䉴䊚䉾䉲䊢䊮䉭䊷䊃䈮䉋䉍㔚᳇⊛䈮䉅ಽ㔌䈘䉏䈩䈇䉎䇯ᓥ䈦䈩䇮䈮䊙䉴䉺䊷䊉䊷䊄䈱㔚䈏ォ 䈚䈩䉅䇮䉴䊧䊷䊑䊉䊷䊄䈱㔚䈱ォ䈲↢䈛䈭䈇䈲䈝䈪䈅䉎䇯䈚䈎䈚䇮䊉䊷䊄㔚䈏GND 䊧䊔䊦䉅䈚 䈒䈲䇮㔚Ḯ䊧䊔䊦䈮ട䈋䈩䇮䊃䊤䊮䉴䊚䉾䉲䊢䊮䉭䊷䊃䈱㑣୯㔚䉕䈋䈩ᄌേ䈚䈩䈚䉁䈉䈫䇮䊃䊤䊮䉴䊚䉾 䉲䊢䊮 䉭䊷䊃䈲䇮ዉㅢ⁁ᘒ䈮䈭䈦䈩䈚䉁䈉䇯ᓥ䈦䈩䇮䉟䉥䊮䈮䉋䉍䊉䊷䊄㔚䈏ᄌേ䈜䉎䈖䈫䈪䇮ਔ ᣇ䈱䊤䉾䉼࿁〝䈏䇮䉝䉾䊒䉶䉾䊃䈜䉎น⢻ᕈ䈏䈅䉎䇯࿑ 3.2.5-4䈮䇮D-䊐䊥䉾䊒䊐䊨䉾䊒࿁〝䈪䈱SET ᔕ╵䈱䉲䊚䊠䊧䊷䉲䊢䊮⚿ᨐ䉕␜䈜䇯SET䊌䊦䉴䈏ᓟ䇮䊙䉴䉺䊷ㇱ䈱䊤䉾䉼䊉䊷䊄䈱㔚䈏㔚Ḯ 䊧䊔䊦䉕䈋䉎䈫䇮䊃䊤䊮䉴䊚䉾䉲䊢䊮 䉭䊷䊃䈱PMOS䈱䉭䊷䊃㔚䈏㑣୯㔚䉕䈋䉎䈢䉄䈮䊃䊤䊮 䉴䊚䉾䉲䊢䊮䉭䊷䊃䈲ዉㅢ䈚䇮䉴䊧䊷䊑䈱䊉䊷䊄䉅䉝䉾䊒䉶䉾䊃䈚䈩䈚䉁䈉䇯
SET䈮ኻ䈜䉎࿁〝䈱⠴ᕈ䈲䇮䊉䊷䊄ኈ㊂䈏ዊ䈘䈒䈭䉎䈾䈬㗼⪺䈮䈭䉎䇯䉁䈢䇮䊃䊤䊮䉳䉴䉺䈱㚟േ㔚 ᵹ䈏ዊ䈘䈒䈭䉎䈖䈫䉅䇮⺃䈘䉏䈢㔚⩄䈱㔚䈏ㆃ䈒䈭䉎䈢䉄䇮SET䈱 ᔨ䉕Ⴧᄢ䈜䉎䇯65nmઍ䈮 䈍䈇䈩䈲䇮䊂䊋䉟䉴䈱㚟േ㔚ᵹ䈲100㱘Aએਅ䈪䈅䉍䇮䉭䊷䊃䈮⸥ᙘ䈘䉏䉎㔚⩄㊂䈲0.8fC䈫ዊ䈘䈇 䈢䉄䇮Ყセ⊛ዊ䈘䈇䉟䉥䊮㔚ᵹ䈮䈍䈇䈩䉅䇮䊌䉴䊃䊤䊮䉳䉴䉺䉕ON⁁ᘒ䈮䈚䈩䈚䉁䈉䈫⠨䈋䉌䉏䉎䇯
䉟䉥䊮䈮䉋䉎䉟䉥䊮㔚ᵹ䈏േ⁁ᘒ䈱䊂䊋䉟䉴䈱㚟േ㔚ᵹ䉋䉍䉅ᄢ䈐䈇㑆䈲䇮࿁〝㔚䈲࿁
ᓳ䈚䈭䈇䇯㊀䉟䉥䊮䈅䉎䈇䈲䇮䊒䊨䊃䊮䈏䈚䈢႐ว䇮ᢔ㔚ᵹ䈏100㱘A䊧䊔䊦䉁䈪ૐਅ䈜䉎䈱 䈮ᤨ㑆䈏䈎䈎䉍䇮⚿ᨐ⊛䈮SET䊌䊦䉴䈲㐳䈒䈭䉎䇯
࿑ 3.2.5-3 䊃䊤䊮䉴䊚䉾䉲䊢䊮䉭䊷䊃䈮䉋䉍᭴ᚑ䈘䉏䉎䊤䉾䉼࿁〝
࿑ 3.2.5-4 SET䈮ኻ䈜䉎䊉䊷䊄䈱ᔕ╵
䉟䉥䊮䈱LET䈭䈬䈮ଐሽ䈜䉎䈏䇮SET䊌䊦䉴䈲䇮1nsecએ⛯䈒น⢻ᕈ䈏䈅䉎䇯
ᦨవ┵䈱CMOS䊁䉪䊉䊨䉳䊷䈪䈲䇮േᵄᢙ䈲ᢙGHz䉕䈋䈩䈇䉎䈱䈪䇮ᢙ䉪䊨䉾䉪䉰䉟䉪䊦䈱 㑆䇮SET䊌䊦䉴䈱⊒↢⁁ᘒ䈏⛯䈒䇯䋨䈖䈱⽎䈲SiGe䊂䊋䉟䉴䈪䈲ታ㛎⊛䈮⏕䈘䉏䈩䈇䉎䇯䋩
䈚䈢䈏䈦䈩䇮SET䈮䉋䉎䉣䊤䊷䈏䇮ᢙᦼ೨䈮↢䈛䈢䉟䉥䊮䈮䉋䉍⊒↢䈜䉎น⢻ᕈ䈏↢䈛䉎䇯 䉁䈢䇮ᢔ㔚ᵹ䈏SET䈱ਥⷐ࿃䈪䈅䉎႐ว䈲䇮䉟䉥䊮䈏䈐䈢䊉䊷䊄䈫䈲䈱㓞ធ䊉䊷䊄䈮㔚⩄
㓸䈏⊒↢䈜䉎䈖䈫䉅䈅䉍䇮৻࿁䈱䉟䉥䊮䈪ⶄᢙ䊉䊷䊄䈮䉣䊤䊷䈏⊒↢䈜䉎䈖䈫䈮䈭䉎䇯 (6) D-FF䈪䈱SEU䈏䈐䉎䉟䉥䊮䈱Timing䈫Critical Charge䈱㑐ଥ㩷
࿑ 3.2.5-5䈮䇮65nm䈱Dဳ䊐䊥䉾䊒䊐䊨䉾䊒䈱࿁〝䈮䈍䈇䈩䇮䊃䊤䊮䉳䉢䊮䊃䊌䊦䉴䈏䈚䈢䈫䈐
䈱䉝䉾䊒䉶䉾䊃䈏䈐䉎ᗵᐲ䉕␜䈜䇯㔚
⩄㊂䈫䇮䊃䊤䊮䉳䉢䊮䊃䊌䊦䉴䈏䈚䈢 䉺 䉟 䊚 䊮 䉫 䈫 䈱 㑐 ଥ 䉕 ⺞ 䈼 䈢 䈏 䇮 ࿑ 3.2.5-5䈮␜䈜䉦䊷䊑䉕䉖䈪䇮䈱 㗔ၞ䈪䈲䇮䉝䉾䊒䉶䉾䊃䈏⊒↢䈜䉎䇯࿑
3.2.5-5(c)䈮ฦ䊐䊥䉾䊒䊐䊨䉾䊒䈱䊉䊷䊄 㔚䈱ᤨ㑆ଐሽᕈ䉕␜䈜䇯䉪䊨䉾䉪䈱 ㆫ⒖䈫䈮䇮䊂䊷䉺䈲1Ბ⋡䈎䉌3Ბ⋡
䈱䊐䊥䉾䊒䊐䊨䉾䊒䈱ฦ䊉䊷䊄䈮㗅ᰴォ ㅍ䈘䉏䉎䇯1Ბ⋡䈱䊐䊥䉾䊒䊐䊨䉾䊒䈮 500psec䈎䉌750psec䈱㑆䈮ㅍ䉌䉏䈢 䊂䊷䉺䈲䇮3Ბ⋡䈱䊐䊥䉾䊒䊐䊨䉾䊒䈮 1750psecᓟ䈮ォㅍ䈘䉏䉎䇯
䉲䊚䊠䊧䊷䉲䊢䊮⸃ᨆ䈮䈍䈇䈩䈲䇮࿑
3.2.5-5(a)䈮␜䈜䉋䈉䈮䇮2Ბ⋡䈱䊐䊥䉾 䊒䊐䊨䉾䊒䈱䊙䉴䉺䊷䈱䊉䊷䊄䈮䇮䉟 䉥䊮ᾖ䈏⊒↢䈜䉎䈫䈚䈩⸃ᨆ䉕ㅴ䉄 䈢䇯࿑ 3.2.5-5(b)䈮䈲䇮䉟䉥䊮䈱 ᾖ䉺䉟䊚䊮䉫䉕6䈱ᤨ㑆㗔ၞ䈮ಽ䈔 䈩䇮䉣䊤䊷䈏⊒↢䈜䉎⏕₸䈫Critical Charge䈱㑐ଥ䉕␜䈚䈢䇯
ᤨ㑆㗔ၞ㸇䈪䈲䇮䊂䊷䉺䈲䉟䉥䊮䉕ฃ䈔䉎2Ბ⋡䈱䊐䊥䉾䊒䊐䊨䉾䊒䈮䈲䇮ㅍ䉌䉏䈩䈇䈭䈇䈱 䈪䇮SET䈲䇮䉟䉥䊮㔚ᵹ䈱ᢔ㔚ᵹ䈱ᓇ㗀䈏ᱷ䉍䇮䉣䊤䊷䈏⊒↢䈜䉎႐ว䈱䉂䈮↢䈛䉎䇯⸃ᨆ 䈮䉋䉎䈫䇮䊂䊷䉺વ䈜䉎㓙䈮䇮䉟䉥䊮㔚ᵹ䈏149±1㱘A䈅䉏䈳䇮SET䈏⊒↢䈜䉎⸘▚⚿ᨐ䈫䈭䈦 䈢䇯
࿑ 3.2.5-5 2GHzേ䈪䈱D-䊐䊥䉾䊒䊐䊨䉾䊒࿁〝䈪 䈱SETᔕ╵
ᤨ㑆㗔ၞ㸈䈲䇮䉪䊨䉾䉪䈏ㆫ⒖䈜䉎䉺䉟䊚䊮䉫䈪䊙䉴䉺䊷䊉䊷䊄䈮䊂䊷䉺䈏ᦠ䈐ㄟ䉁䉏䉎䉺䉟䊚䊮䉫䈪 䉟䉥䊮䈏ᾖ䈜䉎䈱䈪䇮䉅䈦䈫䉅䇮䉣䊤䊷䈮䈭䉎ᗵᐲ䈏㜞䈇ᤨ㑆㗔ၞ䈪䈅䉎䇯
ᤨ㑆㗔ၞ㸉䈲䇮䉁䈘䈮䊙䉴䉺䊷䊉䊷䊄䈮䊂䊷䉺䈏ሽ䈜䉎ᤨ䈮䉟䉥䊮ᾖ䈏⊒↢䈜䉎䈱䈪䉣䊤䊷 ᗵᐲ䈱㜞䈇䉺䉟䊚䊮䉫䈪䈅䉎䇯
ᤨ㑆㗔ၞ㸊䈫㸋䈪䈲䇮䉟䉥䊮ᾖ㔚ᵹ䈏ᄢ䈐䈇႐ว䇮2Ბ⋡䈱䊙䉴䉺䊷䊉䊷䊄䈫䉴䊧䊷䊑䊉䊷䊄䉕 䈧䈭䈓䇮䊃䊤䊮䉴䊚䉾䉲䊢䊮䉭䊷䊃䈏䉟䉥䊮ᾖ䈮䉋䉍ዉㅢ䈚䈩䈇䉎䈢䉄䇮3Ბ⋡䈱䊙䉴䉺䊷䊉䊷䊄䈮䉣 䊤䊷䈏વ䈜䉎䇯
ᤨ㑆㗔ၞ㸌䈪䈲䇮䊂䊷䉺䈲3Ბ⋡䈱䊐䊥䉾䊒䊐䊨䉾䊒䈱䉴䊧䊷䊑䊉䊷䊄䈮ข䉍ㄟ䉁䉏䈩䈇䉎䈢䉄䇮䉣 䊤䊷䈲⊒↢䈚䈭䈇䇯
࿑ 3.2.5-5䈮䈍䈇䈩䇮⭯䈒Ⴃ䉌䉏䈩䈇䉎㗔ၞ䈲䉅䈦䈫䉅䉝䉾䊒䉶䉾䊃䈱ෂ㒾ᐲ䈏㜞䈇䈇ᤨ㑆㗔ၞ䈪
䈅䉎䇯Ớ䈒Ⴃ䉍䈧䈹䈘䉏䈩䈇䉎ᤨ㑆㗔ၞ䈲䇮ᧄ⎇ⓥ䈪ᣂ䈢䈮䈘䉏䈢䊃䊤䊮䉴䊚䉾䉲䊢䊮䉭䊷䊃䈱ዉ ㅢ䈮࿃䈚SET䈏⊒↢䈜䉎䇯䈖䈱ᣂ䈢䈮ട䉒䉎ᤨ㑆䈲䉪䊨䉾䉪ᦼ䈱4ಽ䈱1䈮⋧ᒰ䈜䉎䇯
(7) ⺋䊤䉾䉼䈫䇮Triple Bit Upset Error㩷
࿑ 3.2.5-6(a)䈲4GHz䈱䉪䊨䉾䉪ᵄᢙ 䈪േ䈘䈞䈢႐ว䈱䊙 䊦䉼䊎䉾䊃䉣䊤䊷 (3bit)䈏⊒↢䈜䉎น⢻ᕈ䉕␜䈜䇯䉪䊨䉾䉪
ᵄᢙ䈏Ⴧട䈜䉎䈫䈮䊙䊦䉼䊎䉾䊃䉣䊤䊷 䈱น⢻ᕈ䈲Ⴧട䈜䉎䇯䉟䉥䊮䈏䈐䈢 䊉䊷䊄䈪䈱䊎䉾䊃䈱ォ䈫䈮䇮䊃䊤䊮䉴䊚䉾 䉲䊢䊮䉭䊷䊃䈏ዉㅢ䈜䉎䈖䈫䈪䇮㔚䈱ォ 䈏ᰴᲑ䈮વ䉒䉎䈖䈫䈪䇮SET䈏⊒↢䈜䉎䇯 SET䈏⊒↢䈜䉎䈢䉄䈱䉪䊥䊁䉞䉦䊦䉼䊞䊷 䉳 䈱 㔚 ⩄㊂䈲 ࿑ 3.2.5-6䈮 ␜ 䈚 䈩 䈇 䉎 䇯 250psec䈎䉌750psecઃㄭ䈪䉪䊨䉾䉪䈏ㆫ⒖ 䈜䉎㗔ၞ䈪3bit Error䈏⊒↢䈜䉎น⢻ᕈ 䈏䈅䉎䇯65nmઍ䈮䈍䈇䈩䈲䇮125fC䈱 㔚 ⩄ ㊂ 䈏 䈅 䉏 䈳 䇮3bit䈱 䊙 䊦 䉼 䊎 䉾 䊃 䉣 䊤䊷䈏⊒↢䈜䉎䇯
䈖䈱䈖䈫䈲䇮ᤨ㑆䊄䊜䉟䊮䈪䈱䊥䉻䊮䉻䊮
䉲䊷⊛䈭䉝䊒䊨䊷䉼䈪SET䉕ᛥ䈜䉎䈖䈫䈏䇮ᓟ䈱ᓸ⚦ൻઍ䈮䈲ല䈮䈎䈭䈇䈖䈫䉕␜ໂ䈚 䈩䈇䉎䇯䈖䈱⽎䈲SRAM䈱SET䈮䉅ᓇ㗀䈜䉎䇯䈭䈟䈭䉌䇮SRAM䈪䈲䊃䊤䊮䉴䊚䉾䉲䊢䊮䉭䊷䊃䉕↪
䈇䈩䊎䉾䊃✢䈫䉶䊦䊉䊷䊄䉕ಽ㔌䈚䈩䈇䉎䈎䉌䈪䈅䉎䇯ᓥ䈦䈩䇮䈅䉎䉶䊦䈮䉟䉥䊮䈏䈐䈢႐ว䇮 䊎䉾䊃䊤䉟䊮䈪ㅪ䈭䉎ઁ䉶䊦䈮䉅ᓇ㗀䉕ਈ䈋䇮䉝䉾䊒䉶䉾䊃䈏⊒↢䈜䉎ᕟ䉏䈏䈅䉎䇯䈖䈱⽎䈲䇮ᦨᣂ
࿑ 3.2.5-6 4GHzേᤨ䈱䇮 D-䊐䊥䉾䊒䊐䊨䉾䊒࿁〝䈱SETᔕ╵䇯
ઍ䈮䈍䈇䈩䈲䇮ᷓೞ䈭ᓇ㗀䉕ਈ䈋䉎น⢻ᕈ䈏䈅䉍䇮䈖䈱㗴䉕࿁ㆱ䈜䉎䈮䈲䇮䊃䊤䊮䉴䊚䉾䉲䊢䊮 䉭䊷䊃䉕↪䈇䉎䈼䈐䈪䈲䈭䈇䇯䊄䊧䉟䊮ၮ᧼㑆䈮⊒↢䈜䉎㔚⩄㓸䉕ㆱ䈔䉎䈖䈫䈏䈪䈐䈭䈔䉏䈳䇮䉲 䊮䉫䊦䉟䊔䊮䊃䈏⊒↢䈚䈢䈫䈐䈮䊉䊷䊄㔚䈏䇮㔚Ḯ㔚એ䈮ᄌേ䈜䉎䈖䈫䉕㒐䈓䈖䈫䈲㔍䈚䈇䇯 ᓥ䈦䈩䇮䈖䈱㗴䈎䉌࿁ㆱ䈜䉎䈮䈲࿁〝䈎䉌䊃䊤䊮䉴䊚䉾䉲䊢䊮䉭䊷䊃⥄䉕ข䉍㒰䈐䇮ㅢᏱ䈱䊨䉳䉾 䉪䉭䊷䊃䈣䈔䉕䈉ᔅⷐ䈏䈅䉎䈏䇮ᶖ⾌㔚ജ䉇䇮࿁〝㕙Ⓧ䈏Ⴧᄢ䈚䇮䈠䈱േㅦᐲ䉅ૐਅ䈚䈩䈚䉁䈉 䈪䈅䉐䈉䇯
(8) ⚿⺰㩷
వ┵CMOSᛛⴚ䈮䈍䈇䈩SET䈮䉋䉎⺋䊤䉾䉼⽎䉕㒐ᱛ䈜䉎䈮䈲䇮 䉟䉥䊮䈮䉋䉎SET䊌䊦 䉴䈏ᢙ䉪䊨䉾䉪䉰䉟䉪䊦䈮㆐䈜䉎ലᨐ䉇䇮SET䊌䊦䉴䈏࿁〝㑆䉕વ䈜䉎ലᨐ䉕⠨ᘦ䈮䉏䉎ᔅ ⷐ䈏䈅䉎䇯SET䈏⊒↢䈚䈢႐ว䇮䊉䊷䊄䈱ജ䈏䇮㔚Ḯ䊧䊔䊦䉕䈋䈩ᄌൻ䈚䇮ነ↢䉻䉟䉥䊷䊄䈏 䊐䉤䊪䊷䊄⁁ᘒ䈮䈭䉎䉁䈪䈜䉎䇯䈠䈱⚿ᨐ䇮䊉䊷䊄䈮ធ⛯䈘䉏䈢䊃䊤䊮䉴䊚䉾䉲䊢䊮䉭䊷䊃䈏ዉㅢ⁁
ᘒ䈮⥋䉍䇮㓞ធ䈜䉎䊤䉾䉼䈻䈱⺋ᦠ䈐ㄟ䉂䈏䈐䉎䇯䈖䈱⽎䈲䇮䊜䊝䊥䉇䇮⚵䉂ว䉒䈞⺰ℂ࿁〝䈪 䈱SET䈮䉋䉎䉣䊤䊷䉕Ⴧᄢ䈘䈞䉎䇯䊂䊋䉟䉴䈱േ㔚ᵹ䈏ዊ䈘䈒䈭䉍䇮䉁䈢䇮䊂䊋䉟䉴䈱䊉䊷䊄ኈ㊂䈏 ዊ䈘䈒䈭䉎䈫䇮SET䈱䊌䊦䉴䈲䇮ᢔ㔚ᵹᚑಽ䈮ᓞೣ䈘䉏䉎䇯䈖䈱䈖䈫䈏䇮SET䊌䊦䉴䉕㐳䈒䈚䇮 䉣䊤䊷⏕₸䉕Ⴧട䈘䈞䉎䇯