In an SoC design, a great portion of it is filled with reused IPs. Then, actual test cost information obtained from a past design can be used in a reused portion. Moreover, if possible, an estimation of the test cost information for a new design can be made based on the test cost information of the past design. For example, when there is an actual result value of the scan design of a certain core, it is possible to make an estimation of the test cost information in which the number of the scan chain was changed. If high accuracy is needed, it is necessary to carry out logic synthesis accord- ing to product specification, and to actually perform some scan design. However, if accuracy is not needed, some vari- ations will be created only reflecting the change of the scan chain length when changing the number of scan chains by assuming that the area size, the number of test patterns and the number of flip-flops do not change. In this case, test application time, TAM width, and test data size are easily calculated. It is difficult to estimate the value of power con- sumption with high accuracy. However, there are conven- tional tools, which are able to estimate power consumption for an RTL description, and it is easy to perform relative comparison among two or more DFT(s). On the other hand, newly designed cores that have no past design information need to create the test cost information by actually apply- ing DFT using RTL (a). However, accumulating the actual result value in the test cost information database (e) reduces the cost required to estimate test cost information, and it leads to an increase in accuracy.
As a result of the sharing, the pin overhead decreases to 2. It is also reduced to 1 if Steps 3 and 4 are skipped.
We mention here some differences among the three methods. Since the scan-shift operation is needed in the scan-based methods, at-speed test cannot be performed, i.e., a slow clock is used except in activating delay faults. How- ever, our method can always apply tests at a rated clock speed. In this environment, the IR-drop will be suppressed. Moreover, our method can be performed ﬂexibly accord- ing to a trade-off between hardware overhead and test gen- eration time. The trade-off is determined by the number of constraints used in Step 1 of the proposed method and by the limited processing time per fault in Step 2. In the scan-based methods, all the FFs in a circuit are modiﬁed independently of the circuit function. Consequently, most untestable delay faults in F S l ° F C (Figure 7) are made de-
This paper is organized as follows. Section 2 introduces some basic concepts, such as the data path digraph, and outlines the problems to be solved. Section 3 addresses the power constraints for problem 1, and shows algorithms for performing the test and still meeting the given constraints. Section 4 addresses the same issues for problem 2. Section 5 reports on some experimental results using our proposed schemes. Section 6 concludes with a brief summary.
Figure 2. Proposed scan tree architecture
Figure 2 describes the proposed scan tree architecture. The switch functionality from ST mode to SS mode is carried out by a pattern recognition module, multiplexers and a flip-flop driven by the scan enable signal (in grey color in figure 2). The activation occurs when the last test pattern of the scan tree mode has been applied. This extra DfT logic has a low impact on the area overhead. A MISR is used for the response compression. Figure 3 presents the two configurations of the architecture: in 3.a the ST mode and in 3.b the SS mode. In both cases, there is only one scan input and one scan output and a single test control input.
ステップ 2 で生成した組合せ回路要素 M に対する 観測経路が 2 入力演算モジュール M j を通る場合を考 える．観測経路が M jの非伝搬入力 x 上を通る場合，
M jの伝搬入力 x と出力ポート z 間にスルー機能が ない場合には，任意の値を伝搬できない．ここで， M jの y に定数を与えて x–z 間のスルー機能を実現でき る場合について考える．外部入力から M jの y へ定 数を印加 できれば， M jの x–z 間のス ルー機能を 新 たに付加する必要はないので，スルー機能実現のため
Figure 3: Outline of the method.
results of these pre-processes are used when selecting instructions for templates or setting a target fault cov- erage at later steps. Then we repeatedly generate tem- plates as follows. We ﬁrst generate a template of a test program for a sequential module under test, and extract an input temporal spatial constraint from the template. We apply sequential ATPG to the module with the ex- tracted constraint and obtain test sequence. Finally, we obtain values of operands from the test sequence. We repeat this process until achieving acceptable fault cov- erage or trying all the generated templates.
The use of SoC design methodology introduces sev- eral new problems and challenges in testing . First, the cores that are embedded deep inside the silicon chip require a Test Access Mechanisms (TAM) for test data transporta- tion. Several TAM architectures have been proposed such as TestRail , Virtual TAM , and TAMs based on trans- parency . Second, the SoC’s core-based design requires a mechanism to isolate the cores during test. This is achieved by the use of core wrappers , . Third, the cores can either be tested sequentially at the cost of longer test appli-