MOSFET – Power, Single, P-Channel, DPAK
-60 V, -15.5 A
Features
• Withstands High Energy in Avalanche and Commutation Modes
• Low Gate Charge for Fast Switching
• AEC Q101 Qualified − NTDV20P06L
• These Devices are Pb−Free and are RoHS Compliant
Applications• Bridge Circuits
• Power Supplies, Power Motor Controls
• DC−DC Conversion
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter Symbol Value Unit
Drain−to−Source Voltage VDSS −60 V
Gate−to−Source
Voltage Continuous VGS $20 V
Non−Repetitive tp v10 ms VGSM $30 Continuous
Drain Current Steady State TC = 25°C ID −15.5 A Power Dissipa-
tion Steady State TC = 25°C PD 65 W
Pulsed Drain
Current tp = 10 ms IDM $50 A
Operating Junction and Storage Temperature TJ,
TSTG −55 to
175 °C
Single Pulse Drain−to−Source Avalanche Energy (VDD = 25 V, VGS = 5 V, IPK = 15 A, L = 2.7 mH, RG = 25 W)
EAS 304 mJ
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s) TL 260 °C
THERMAL RESISTANCE RATINGS
Parameter Symbol Max Unit
Junction−to−Case (Drain) RqJC 2.3 °C/W
Junction−to−Ambient – Steady State (Note 1) RqJA 80 Junction−to−Ambient – Steady State (Note 2) RqJA 110
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.
P−Channel D
S G
Gate1 3 Source 2
Drain Drain4
DPAK CASE 369C
STYLE 2
MARKING DIAGRAMS
20P06L Device Code A = Assembly Location
Y = Year
WW = Work Week
1 2 3 4
1
Gate 3
Source 2
Drain 4 Drain
IPAK/DPAK CASE 369D STYLE 2
12 3
4
−60 V 130 mW @ −5.0 V
ID MAX (Note 1) V(BR)DSS
AYWW T20 P06LG
AYWW T20 P06LG
RDS(on) TYP
−15.5 A www.onsemi.com
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Parameter Symbol Test Condition Min Typ Max Units
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = −250 mA −60 −74 V Drain−to−Source Breakdown Voltage
Temperature Coefficient V(BR)DSS/TJ −64 mV/°C
Zero Gate Voltage Drain Current IDSS VGS = 0 V, VDS = −60 V
TJ = 25°C −1.0 mA
TJ = 150°C −10
Gate−to−Source Leakage Current IGSS VDS = 0 V, VGS = ±20 V ±100 nA
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = −250 mA −1.0 −1.5 −2.0 V
Gate Threshold Temperature Coefficient VGS(TH)/TJ 3.1 mV/°C
Drain−to−Source On Resistance RDS(on) VGS = −5.0 V, ID = −7.5 A 0.130 0.150 W VGS = −5.0 V, ID = −15 A 0.143
Forward Transconductance gFS VDS = −10 V, ID = −7.5 A 11 S
Drain−to−Source On−Voltage VDS(on) VGS = −5.0 V, ID = −7.5 A
TJ = 25°C −1.2 V
TJ = 150°C −1.9
CHARGES AND CAPACITANCES
Input Capacitance CISS
VGS = 0 V, f = 1 MHz, VDS = −25 V
740 1190 pF
Output Capacitance COSS 207 300
Reverse Transfer Capacitance CRSS 66 120
Total Gate Charge QG(TOT)
VGS = −5.0 V, VDS = −48 V, ID = −18 A
15 26 nC
Gate−to−Source Charge QGS 4.0
Gate−to−Drain Charge QGD 7.0
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time td(ON)
VGS = −5.0 V, VDD = −30 V, ID = −15 A, RG = 9.1 W
11 20 ns
Rise Time tr 90 180
Turn−Off Delay Time td(OFF) 28 50
Fall Time tf 70 135
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage VSD
VGS = 0 V, IS = −15 A TJ = 25°C 1.5 2.5 V
TJ = 150°C 1.3
Reverse Recovery Time tRR
VGS = 0 V, dIS/dt = 100 A/ms, IS = −12 A
60 ns
Charge Time ta 39
Discharge Time tb 21
Reverse Recovery Charge QRR 0.13 nC
3. Pulse Test: pulse width v 300 ms, duty cycle v 2%
4. Switching characteristics are independent of operating junction temperatures
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
0 5 10 15 20 25 30 35 40
0 1 2 3 4 5 6 7 8 9 10
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
−ID, DRAIN CURRENT (A)
Figure 1. On−Region Characteristics VGS = −6 V
VGS = −5.5 V VGS = −5 V VGS = −4.5 V VGS = −4 V VGS = −3.5 V VGS = −3 V VGS = −10 V
VGS = −9 V VGS = −8 V VGS = −7 V
TJ = 25°C 0 10 20 30 40
0 1 2 3 4 5 6 7 8 9
−VDS, GATE−TO−SOURCE VOLTAGE (V) Figure 2. Transfer Characteristics
−ID, DRAIN CURRENT (A)
TJ = 25°C TJ = −55°C
TJ = 125°C
VDS w 10 V
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
0 5 10 15 20 25 30
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
Figure 3. On−Resistance versus Drain Current and Temperature
−ID, DRAIN CURRENT (A) TJ = 125°C
TJ = 25°C TJ = −55°C VGS = −5 V
0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2 0.225 0.25
0 3 6 9 12 15 18 21 24
VGS = −5 V VGS = −10 V TJ = 25°C
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
Figure 4. On−Resistance versus Drain Current and Gate Voltage
−ID, DRAIN CURRENT (A)
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
, DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
ID = −7.5 A VGS = −5 V
10 100 1000 10000
−ID, LEAKAGE (nA)
TJ = 125°C TJ = 150°C VGS = 0 V
TYPICAL PERFORMANCE CURVES
(TJ = 25°C unless otherwise noted)
0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400
−10 −5 0 5 10 15 20 25
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V)
Figure 7. Capacitance Variation VGS = 0 V
C, CAPACITANCE (pF)
VDS = 0 V TJ = 25°C
Ciss Coss Crss Ciss
Crss
−VGS −VDS
0 1.25 2.5 3.75 5.0 6.25 7.5
0 4 8 12 16
0 10 20 30 40 50 60
Qg, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source and Drain−to−Source Voltage versus Total Charge
−VGS, GATE−TO−SOURCE VOLTAGE (V)
QG
QGD
Qgs
VDS
VGS
ID = −15 A TJ = 25°C (V) DSV, DRAIN−TO−SOURCE VOLTAGE
1 10 100 1000
1 10 100
t, TIME (nS)
tR
tF td(off)
td(on) VDD = −30 V
ID = −15 A VGS = −5 V
Rg, GATE RESISTANCE (W)
Figure 9. Resistive Switching Time Variation versus Gate Resistance
0 5 10 15 20
0 0.25 0.5 0.75 1 1.25 1.5 1.75
−IS, SOURCE CURRENT (A)
−VSD, SOURCE−TO−DRAIN VOLTAGE (V) Figure 10. Diode Forward Voltage versus
Current VGS = 0 V
TJ = 25°C
0.1 1 10 100 1000
0.1 1 10 100
−VDS, DRAIN−TO−SOURCE VOLTAGE (V)
−ID, DRAIN CURRENT (A)
Figure 11. Maximum Rated Forward Biased Safe Operating Area
100 1 10 ms
dc VGS = −15 V
Single Pulse TC = 25°C
RDS(on) Limit Thermal Limit Package Limit
0 50 100 150 200 250 300 350
25 50 75 100 125 150
TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature ID = −15 A
EAS, SINGLE PULSE DRAIN−TO−SOURCE AVALANCHE ENERGY (mJ)
0.01 0.1 10
0.000001 0.00001 0.0001 0.001 0.01 0.1 1
Figure 13. Thermal Response t, TIME (s)
Rqjc(°C/W), EFFECTIVE TRANSIENT THERMAL RESPONSE
Single Pulse 1
0.1 0.2
0.02 D = 0.5
0.05
0.01
ORDERING INFORMATION
Device Package Shipping†
NTD20P06LG
(Pb−Free)DPAK
75 Units / Rail
NTD20P06LT4G 2500 / Tape & Reel
NTDV20P06LT4G 2500 / Tape & Reel
NTDV20P06LT4G−VF01 2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
SCALE 1:1
STYLE 1:
PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR
STYLE 2:
PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN
STYLE 3:
PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE
STYLE 4:
PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE STYLE 5:
PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE
1 2 3
4
V
S A
K
−T−
SEATING PLANE
R B
F
G
D3 PL
0.13 (0.005)M T C
E
J
H
DIM MIN MAX MIN MAX MILLIMETERS INCHES
A 0.235 0.245 5.97 6.35 B 0.250 0.265 6.35 6.73 C 0.086 0.094 2.19 2.38 D 0.027 0.035 0.69 0.88 E 0.018 0.023 0.46 0.58 F 0.037 0.045 0.94 1.14
G 0.090 BSC 2.29 BSC
H 0.034 0.040 0.87 1.01 J 0.018 0.023 0.46 0.58 K 0.350 0.380 8.89 9.65 R 0.180 0.215 4.45 5.45 S 0.025 0.040 0.63 1.01 V 0.035 0.050 0.89 1.27
STYLE 6:
PIN 1. MT1 2. MT2 3. GATE 4. MT2
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
Z
Z 0.155 −−− 3.93 −−−
STYLE 7:
PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR
xxxxxxxxx = Device Code A = Assembly Location lL = Wafer Lot
Y = Year
WW = Work Week YWW
xxxxxxxx
xxxxx ALYWW
x Discrete
Integrated Circuits CASE 369D−01IPAK
ISSUE C
DATE 15 DEC 2010
MARKING DIAGRAMS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
98AON10528D DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1 IPAK (DPAK INSERTION MOUNT)
DPAK (SINGLE GAUGE) CASE 369C
ISSUE F
DATE 21 JUL 2015 SCALE 1:1
STYLE 1:
PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR
STYLE 2:
PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN
STYLE 3:
PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE
STYLE 4:
PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE
STYLE 5:
PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE STYLE 6:
PIN 1. MT1 2. MT2 3. GATE 4. MT2
STYLE 7:
PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR
1 2 3 4
STYLE 8:
PIN 1. N/C 2. CATHODE 3. ANODE 4. CATHODE
STYLE 9:
PIN 1. ANODE 2. CATHODE 3. RESISTOR ADJUST 4. CATHODE
STYLE 10:
PIN 1. CATHODE 2. ANODE 3. CATHODE 4. ANODE
b D E
b3
L3
L4 b2
0.005 (0.13)M C
c2 A
c
C
Z
DIM MIN MAX MIN MAX MILLIMETERS INCHES
D 0.235 0.245 5.97 6.22 E 0.250 0.265 6.35 6.73 A 0.086 0.094 2.18 2.38 b 0.025 0.035 0.63 0.89
c2 0.018 0.024 0.46 0.61 b2 0.028 0.045 0.72 1.14 c 0.018 0.024 0.46 0.61
e 0.090 BSC 2.29 BSC b3 0.180 0.215 4.57 5.46
L4 −−− 0.040 −−− 1.01 L 0.055 0.070 1.40 1.78
L3 0.035 0.050 0.89 1.27
Z 0.155 −−− 3.93 −−−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI- MENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H.
7. OPTIONAL MOLD FEATURE.
1 2 3
4
XXXXXX = Device Code A = Assembly Location
L = Wafer Lot
Y = Year
WW = Work Week
G = Pb−Free Package AYWW XXX XXXXXG XXXXXXG
ALYWW
Discrete IC
5.80 0.228
2.58 0.102
1.60 0.063 6.20
0.244
3.00 0.118
6.17 0.243
ǒ
inchesmmǓ
SCALE 3:1
GENERIC MARKING DIAGRAM*
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
H 0.370 0.410 9.40 10.41 A1 0.000 0.005 0.00 0.13
L1 0.114 REF 2.90 REF L2 0.020 BSC 0.51 BSC
A1
H
DETAIL A
SEATING PLANE
A
B
C
L1 L
H L2GAUGEPLANE
DETAIL A
ROTATED 90 CW5
e BOTTOM VIEW
Z
BOTTOM VIEW SIDE VIEW
TOP VIEW
ALTERNATE CONSTRUCTIONS NOTE 7
Z
*This information is generic. Please refer to device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking.
information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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