MOSFET – Single, N-Channel, Logic Level, SO-8 FL

N-Channel, Logic Level, SO-8 FL

30 V, 1.15 m W , 230 A

NTMFS4C302N

Features

• Small Footprint (5x6 mm) for Compact Design

• ^{Low R}

to Minimize Conduction Losses

• ^{Low Q}

and Capacitance to Minimize Driver Losses

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant

MAXIMUM RATINGS (T_J = 25°C unless otherwise noted)

Parameter Symbol Value Unit

Drain−to−Source Voltage V_DSS 30 V

Gate−to−Source Voltage V_GS "20 V

Continuous Drain Cur- rent R_qJC (Notes 1, 2,

3) Steady

State

T_C = 25°C I_D 230 A

Power Dissipation

R_qJC (Notes 1, 2) T_C = 25°C P_D 96 W

Continuous Drain Cur- rent R_qJA (Notes 1, 2,

3) Steady

State

T_A = 25°C I_D 41 A

Power Dissipation

R_qJA (Notes 1, 2) T_A = 25°C P_D 3.13 W

Pulsed Drain Current T_A = 25°C, tp = 10 ms I_DM 900 A Operating Junction and Storage Temperature T_J, T_stg −55 to

150 °C

Source Current (Body Diode) @ 10 ms IS 128 A Single Pulse Drain−to−Source Avalanche

Energy (I_L(pk) = 61 A) EAS 186 mJ

Lead Temperature for Soldering Purposes

(1/8″ from case for 10 s) T_L 260 °C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

THERMAL RESISTANCE MAXIMUM RATINGS (Note 1)

Parameter Symbol Value Unit

Junction−to−Case − Steady State (Note 2) R_qJC 1.3 °C/W Junction−to−Ambient − Steady State (Note 2) R_qJA 40

1. The entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted.

2. Surface−mounted on FR4 board using a 650 mm², 2 oz. Cu pad.

3. Maximum current for pulses as long as 1 second is higher but is dependent on pulse duration and duty cycle.

SO−8 FLAT LEAD CASE 488AA

STYLE 1

MARKING DIAGRAM www.onsemi.com

4C02N AYWZZ

1

V_(BR)DSS R_DS(on) MAX I_D MAX 30 V 1.15 mW @ 10 V

230 A 1.7 mW @ 4.5 V

G (4)

S (1,2,3) N−CHANNEL MOSFET

D (5,6)

S S S G

D

D D

D

Device Package Shipping^† ORDERING INFORMATION

NTMFS4C302NT1G SO−8 FL

(Pb−Free) 1500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

4C02N = Specific Device Code A = Assembly Location

Y = Year

W = Work Week ZZ = Lot Traceabililty

NTMFS4C302NT3G SO−8 FL

(Pb−Free) 5000 / Tape & Reel

Parameter Symbol Test Condition Min Typ Max Unit OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage V(BR)DSS VGS = 0 V, ID = 250 mA 30 V

Drain−to−Source Breakdown Voltage

Temperature Coefficient V(BR)DSS/

T_J 24 mV/°C

Zero Gate Voltage Drain Current I_DSS V_GS = 0 V,

V_DS = 24 V T_J = 25 °C 1.0

T_J = 125°C 100 mA

Gate−to−Source Leakage Current I_GSS V_DS = 0 V, V_GS = 20 V 100 nA

ON CHARACTERISTICS (Note 4)

Gate Threshold Voltage V_GS(TH) V_GS = V_DS, I_D = 250 mA 1.3 2.2 V

Negative Threshold Temperature Coefficient V_GS(TH)/T_J 5.8 mV/°C

Drain−to−Source On Resistance R_DS(on) V_GS = 10 V I_D = 30 A 0.95 1.15

V_GS = 4.5 V I_D = 30 A 1.35 1.7 mW

Forward Transconductance g_FS V_DS = 3 V, I_D = 30 A 135 S

Gate Resistance R_G T_A = 25 °C 0.75 W

CHARGES AND CAPACITANCES

Input Capacitance C_ISS

VGS = 0 V, f = 1 MHz, VDS = 15 V

5780

Output Capacitance C_OSS 2320 pF

Reverse Transfer Capacitance C_RSS 70

Total Gate Charge Q_G(TOT)

V_GS = 4.5 V, V_DS = 15 V; I_D = 30 A

37

Threshold Gate Charge Q_G(TH) 9.0 nC

Gate−to−Source Charge Q_GS 16

Gate−to−Drain Charge Q_GD 7.0

Total Gate Charge QG(TOT) VGS = 10 V, VDS = 15 V,

I_D = 30 A 82 nC

SWITCHING CHARACTERISTICS (Note 5)

Turn−On Delay Time t_d(ON)

VGS = 4.5 V, VDS = 15 V, ID = 15 A, R_G = 3.0 W

20

Rise Time t_r 19 ns

Turn−Off Delay Time t_d(OFF) 42

Fall Time t_f 11

DRAIN−SOURCE DIODE CHARACTERISTICS

Forward Diode Voltage V_SD VGS = 0 V,

I_S = 10 A

T_J = 25°C 0.75 1.1

T_J = 125°C 0.6 V

Reverse Recovery Time t_RR

V_GS = 0 V, dI_S/dt = 100 A/ms, I_S = 30 A

56

Charge Time t_a 29 ns

Discharge Time t_b 27

Reverse Recovery Charge Q_RR 69 nC

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

4. Pulse Test: pulse width v 300 ms, duty cycle v 2%.

5. Switching characteristics are independent of operating junction temperatures.

TYPICAL CHARACTERISTICS

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics V_DS, DRAIN−TO−SOURCE VOLTAGE (V) V_GS, GATE−TO−SOURCE VOLTAGE (V)

3 1.5

1 0.5 00

100 200 150

4.0 3.5

3.0 2.0

1.5

Figure 3. On−Resistance vs. V_GS Figure 4. On−Resistance vs. Drain Current and Gate Voltage

V_GS, GATE−TO−SOURCE VOLTAGE (V) I_D, DRAIN CURRENT (A)

9 8

7 10

6 5 4 0.753

1.15 1.55

450 350

250 300 400

200 1.15

1.55 2.15

0.75

T, JUNCTION TEMPERATURE (°C) V , DRAIN−TO−SOURCE VOLTAGE (V)

125 100 75 25

0

−25

−50 0.8 1.0 1.1 1.3

30 25 20

15 10

100 100 1000 10000

ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A)

RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW) RDS(on), DRAIN−TO−SOURCE RESISTANCE (mW)

RDS(on), DRAIN−TO−SOURCE RESISTANCE (NORMALIZED) IDSS, LEAKAGE (nA)

50

4.5 V

3.5 V

3.1 V 2.9 V 2.7 V 2.5 V 3.7 V

T_J = 25°C VDS = 3 V

TJ = 25°C

TJ = 125°C

T_J = −55°C

1.35

1.95 T_J = 25°C

I_D = 30 A

V_GS = 4.5 V T_J = 25°C

VGS = 10 V

50 V_GS = 10 V

I_D = 30 A

VGS = 0 V

TJ = 85°C T_J = 150°C TJ = 125°C 2.5

0.95 1.95 1.75

1.2 1.4

0.7 1.5 450

2.15

150 3.3 V

2 0

100 200 300

150 350

50 250 450

2.35

0.95

1.6

0.9

4.5 250

300 350

400 4.0 V

1.35 1.75 2.35 2.5

400

100 50 0

150 100000

T_J = 100°C

5 10 V 6 V

Q_gs

Figure 7. Capacitance Variation Figure 8. Gate−to−Source and Drain−to−Source Voltage vs. Total Charge

V_DS, DRAIN−TO−SOURCE VOLTAGE (V) Q_g, TOTAL GATE CHARGE (nC)

25 20

15

10 30

5 100

100

Figure 9. Resistive Switching Time Variation vs. Gate Resistance

RG, GATE RESISTANCE (W)

100 10

11 10 100 1000

C, CAPACITANCE (pF) VGS, GATE−TO−SOURCE VOLTAGE (V)

t, TIME (ns)

V_GS = 0 V TJ = 25°C f = 1 MHz

C_iss C_oss

Crss

QT

Qgd

VGS = 4.5 V V_DD = 15 V I_D = 15 A

td(off)

t_d(on) t_r t_f 1000

10000

0 2 4 6 8 11

0 20 30 40 60 70 80 90

VDS = 15 V ID = 30 A TJ = 25°C 50

10 1 3 5 7 9

Figure 10. Diode Forward Voltage vs. Current V_SD, SOURCE−TO−DRAIN VOLTAGE (V)

0.9 0.8 0.7 0.6 0.5 0.1 0.4

1 10

IS, SOURCE CURRENT (A)

T_J = 25°C T_J = −55°C V_GS = 0 V

1.0 100

1000

0.1 1 10 100 1000

0.01 1 10 100

Figure 11. Maximum Rated Forward Biased V_DS, DRAIN−TO−SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)

VGS < 10 V Single Pulse TC = 25°C R_DS(on) Limit Thermal Limit Package Limit

100 ms

10 ms 1 ms

dc 10

0.3

0.2 1.1

T_J = 175°C

TJ = 150°C

0.1

TYPICAL CHARACTERISTICS

Figure 12. Thermal Response PULSE TIME (sec)

0.01 0.001

0.0001 0.00001

0.000001 0.001

0.1 1 10 100

R(t) (°C/W)

0.1 1 10 100 1000

10%

Duty Cycle = 50%

20%

5%

2%

1%

Single Pulse 0.01

R_qJA Steady State = 40°C/W

1 10 100 1000

1.0E−6 10E−6 100E−6 10E−3

Figure 13. Maximum Drain Current vs. Time in Avalanche

TIME IN AVALANCHE (S) IPEAK, DRAIN CURRENT (A)

T_J = 25°C T_J = 100°C

1.0E−3

M 3.00 3.40 q 0 _ −−− ^3.8012 _ (SO−8FL)

CASE 488AA ISSUE N

DATE 25 JUN 2018 SCALE 2:1

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD FLASH PROTRUSIONS OR GATE BURRS.

XXXXXX = Specific Device Code A = Assembly Location

Y = Year

W = Work Week

ZZ = Lot Traceability

1 2 3 4

TOP VIEW

SIDE VIEW

BOTTOM VIEW D1

E1 q

D

E 2

2 B A

0.20 C

0.20 C

2 X

2 X

DIM MIN NOM MILLIMETERS A 0.90 1.00 A1 0.00 −−−

b 0.33 0.41 c 0.23 0.28

D 5.15

D1 4.70 4.90 D2 3.80 4.00

E 6.15

E1 5.70 5.90 E2 3.45 3.65

e 1.27 BSC

G 0.51 0.575

K 1.20 1.35

L 0.51 0.575

L1 0.125 REF

A 0.10 C

0.10 C

DETAIL A

1 4

L1 e/2

8X

G D2 E2

K b

A 0.10 C B 0.05 c

L

DETAIL A c A1

4 X

C

SEATING PLANE

GENERIC MARKING DIAGRAM*

1

XXXXXX AYWZZ 1

MAX 1.10 0.05 0.51 0.33 5.10 4.20 6.10 3.85 0.71 1.50 0.71

STYLE 1:

PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN

M

*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

1.270

2X

0.750 1.000 0.905

4.530 1.530

4.560 0.495

3.200

1.330

0.965

2X 2X

4X 4X PIN 5

(EXPOSED PAD)

STYLE 2:

PIN 1. ANODE 2. ANODE 3. ANODE 4. NO CONNECT 5. CATHODE

5.00 5.30

6.00 6.30

PITCH

DIMENSIONS: MILLIMETERS

1

RECOMMENDED e

2X

0.475

*This information is generic. Please refer to device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Some products may not follow the Generic Marking.

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

98AON14036D DOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 1 DFN5 5x6, 1.27P (SO−8FL)

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