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MMBF4391L, MMBF4392L, MMBF4393L JFET Switching Transistors

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MMBF4393L

JFET Switching Transistors

N−Channel

Features

• S Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant

MAXIMUM RATINGS

Rating Symbol Value Unit

Drain−Source Voltage V

DS

30 Vdc

Drain−Gate Voltage V

DG

30 Vdc

Gate−Source Voltage V

GS

30 Vdc

Forward Gate Current I

G(f)

50 mAdc

THERMAL CHARACTERISTICS

Characteristic Symbol Max Unit

Total Device Dissipation FR− 5 Board (Note 1) T

A

= 25°C

Derate above 25°C

P

D

225 1.8 mW mW/°C Thermal Resistance, Junction−to−Ambient R

qJA

556 °C/W Junction and Storage Temperature Range T

J

, T

stg

−55 to +150 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

1. FR− 5 = 1.0 0.75 0.062 in.

SOT−23 CASE 318 STYLE 10

See detailed ordering, marking and shipping information in the package dimensions section on page 2 of this data sheet.

MARKING & ORDERING INFORMATION www.onsemi.com

2 SOURCE

3 GATE

1 DRAIN

XXX = Specific Device Code M = Date Code*

G = Pb−Free Package

*Date Code orientation and/or overbar may vary depending upon manufacturing location.

(Note: Microdot may be in either location) MARKING DIAGRAM

1

XXX M G G 2 1

3

(2)

www.onsemi.com 2

ELECTRICAL CHARACTERISTICS (T

A

= 25°C unless otherwise noted)

Characteristic Symbol Min Max Unit

OFF CHARACTERISTICS Gate−Source Breakdown Voltage

(I

G

= 1.0 mAdc, V

DS

= 0) V

(BR)GSS

30 − Vdc

Gate Reverse Current

(V

GS

= 15 Vdc, V

DS

= 0, T

A

= 25°C) (V

GS

= 15 Vdc, V

DS

= 0, T

A

= 100°C)

I

GSS

− − 1.0

0.20 nAdc

mAdc Gate−Source Cutoff Voltage

(V

DS

= 15 Vdc, I

D

= 10 nAdc) MMBF4391LT1

MMBF4392LT1 MMBF4393LT1

V

GS(off)

−4.0 −2.0

−0.5

−5.0 −10

−3.0

Vdc

Off−State Drain Current

(V

DS

= 15 Vdc, V

GS

= −12 Vdc)

(V

DS

= 15 Vdc, V

GS

= −12 Vdc, T

A

= 100°C)

I

D(off)

− − 1.0

1.0 nAdc

mAdc ON CHARACTERISTICS

Zero−Gate−Voltage Drain Current (V

DS

= 15 Vdc, V

GS

= 0)

MMBF4391LT1 MMBF4392LT1 MMBF4393LT1

I

DSS

50 25 5.0

150 75 30

mAdc

Drain−Source On−Voltage (I

D

= 12 mAdc, V

GS

= 0)

MMBF4391LT1 (I

D

= 6.0 mAdc, V

GS

= 0)

MMBF4392LT1 (I

D

= 3.0 mAdc, V

GS

= 0)

MMBF4393LT1

V

DS(on)

0.4 0.4 0.4

Vdc

Static Drain−Source On−Resistance (I

D

= 1.0 mAdc, V

GS

= 0)

MMBF4391LT1 MMBF4392LT1 MMBF4393LT1

r

DS(on)

− −

30 60 100

W

SMALL− SIGNAL CHARACTERISTICS Input Capacitance

(V

DS

= 0 Vdc, V

GS

= −15 Vdc, f = 1.0 MHz) C

iss

− 14 pF

Reverse Transfer Capacitance

(V

DS

= 0 Vdc, V

GS

= −12 Vdc, f = 1.0 MHz) C

rss

− 3.5 pF

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

ORDERING INFORMATION

Device Marking Package Shipping

MMBF4391LT1G 6J

SOT−23

(Pb−Free) 3,000 / Tape & Reel

SMMBF4391LT1G* 6J

MMBF4392LT1G 6K

MMBF4393LT1G M6G

SMMBF4393LT1G* M6G

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

(3)

TYPICAL CHARACTERISTICS

TJ = 25°C

I

D

, DRAIN CURRENT (mA) , TURN-ON DELA Y TIME (ns) d(on) t

5.0 2.0 20 10

0.5 1.0 3.0 5.0 7.0

1.0 50 100

0.7 2.0 10 20

I

D

, DRAIN CURRENT (mA) , RISE TIME (ns) r t

Figure 1. Turn−On Delay Time Figure 2. Rise Time

RK = RD'

RK = 0

RK = RD'

RK = 0

I

D

, DRAIN CURRENT (mA) , TURN-OFF DELA Y TIME (ns) d(of f) t

Figure 3. Turn−Off Delay Time

RK = RD'

RK = 0

I

D

, DRAIN CURRENT (mA) Figure 4. Fall Time

RK = RD'

RK = 0

, F ALL TIME (ns) f t

MMBF4391 MMBF4392 MMBF4393

30 50 200

500 1000

0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 5.0

2.0 20 10

1.0 50 100 200 500 1000

0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50 0.5 0.7 1.0 2.0 3.0 5.0 7.0 10 20 30 50

5.0 2.0 20 10

1.0 50 100 200 500 1000

5.0 2.0 20 10

1.0 50 100 200 500 1000

TJ = 25°C MMBF4391 MMBF4392 MMBF4393

TJ = 25°C MMBF4391 MMBF4392 MMBF4393

TJ = 25°C MMBF4391 MMBF4392 MMBF4393 VGS(off) = 12 V

= 7.0 V

= 5.0 V

VGS(off) = 12 V

= 7.0 V

= 5.0 V

VGS(off) = 12 V

= 7.0 V

= 5.0 V VGS(off) = 12 V

= 7.0 V

= 5.0 V

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www.onsemi.com 4

Figure 5. Switching Time Test Circuit

Figure 6. Typical Forward Transfer Admittance Figure 7. Typical Capacitance I

D

, DRAIN CURRENT (mA)

2.0 5.0

3.0 7.0

0.5 1.0 3.0 5.0 7.0 30 50

10 20

0.7 2.0 10 20

, FOR W ARD TRANSFER ADMITT ANCE (mmhos) fs V

10

2.0 15

3.0 5.0 7.0

0.5 1.0 3.0 5.0 30

0.3

0.1 10

0.05 0.03

V

R

, REVERSE VOLTAGE (VOLTS)

C, CAP ACIT ANCE (pF)

Tchannel = 25°C

VDS = 15 V Tchannel = 25°C

(Cds is negligible Cgs

V

DD

V

GG

R

GG

R

T

R

GEN

50 W V

GEN

R

K

R

D

OUTPUT INPUT

50 W

50 W

SET VDS(off) = 10 V

INPUT PULSE tr≤ 0.25 ns tf ≤ 0.5 ns PULSE WIDTH = 2.0 ms DUTY CYCLE ≤ 2.0%

RGG > RK RD' = RD(RT + 50)

RD + RT + 50

Figure 8. Effect of Gate−Source Voltage on Drain−Source Resistance 80

120 160 200

50

1.0 2.0 3.0 5.0 -70 -40 -10 20 80 140 170

V

GS

, GATE-SOURCE VOLTAGE (VOLTS)

r

4.0 0

40

100 mA 125 mA 75 mA

50 mA 25 mA IDSS

= 10 mA

Tchannel = 25°C

Figure 9. Effect of Temperature on Drain−Source On−State Resistance

1.8

1.0 2.0

1.2 1.4 1.6

0.8 0.6 0.4

ID = 1.0 mA VGS = 0

, DRAIN-SOURCE ON-ST A T E DS(on) RESIST ANCE (NORMALIZED)

T

channel

, CHANNEL TEMPERATURE ( ° C) 1.5

1.0

Cgd

110 6.0 7.0 8.0

0 r , DRAIN-SOURCE ON-ST A T E DS(on) RESIST ANCE (OHMS)

MMBF4393

MMBF4392

MMBF4391

NOTE 1

The switching characteristics shown above were measured using a test circuit similar to Figure 5. At the beginning of the switching interval, the gate voltage is at Gate Supply Voltage (−V GG ). The Drain−Source Voltage (V DS ) is slightly lower than Drain Supply Voltage (V DD ) due to the voltage divider. Thus Reverse Transfer Capacitance (C rss ) of Gate−Drain Capacitance (C gd ) is charged to V GG + V DS .

During the turn−on interval, Gate−Source Capacitance (C gs ) discharges through the series combination of R Gen and R K . C gd must discharge to V DS(on) through R G and R K in series with the parallel combination of effective load impedance (R’ D ) and Drain−Source Resistance (r DS ). During the turn−off, this charge flow is reversed.

Predicting turn−on time is somewhat difficult as the channel resistance r DS is a function of the gate−source voltage. While C gs

discharges, V GS approaches zero and r DS decreases. Since C gd

discharges through r DS , turn−on time is non−linear. During turn−off, the situation is reversed with r DS increasing as C gd charges.

The above switching curves show two impedance conditions; 1)

R K is equal to R D’ which simulates the switching behavior of

cascaded stages where the driving source impedance is normally the

load impedance of the previous stage, and 2) R K = 0 (low

impedance) the driving source impedance is that of the generator.

(5)

Figure 10. Effect of I

DSS

on Drain−Source Resistance and Gate−Source Voltage

I

DSS

, ZERO-GATE VOLTAGE DRAIN CURRENT (mA) , DRAIN-SOURCE ON-ST A T E DS(on)r

20 10 30 40 50

30 40 50 60 70 20

RESIST ANCE (OHMS)

0 10

0 1.0 2.0 3.0 4.0 5.0

, GA TE-SOURCE VOL TAGE GS V (VOL TS)

Tchannel = 25°C

VGS(off) rDS(on) @ VGS = 0

6.0 7.0 8.0 9.0 10

70 60 80 90 100

80 90 100 110 120 130 140 150

NOTE 2

The Zero−Gate−Voltage Drain Current (I DSS ) is the principle determinant of other J−FET characteristics.

Figure 10 shows the relationship of Gate−Source Off Voltage (V GS(off) ) and Drain−Source On Resistance (r DS(on) ) to I DSS . Most of the devices will be within

±10% of the values shown in Figure 10. This data will be useful in predicting the characteristic variations for a given part number.

For example:

Unknown

r DS(on) and V GS range for an MMBF4392

The electrical characteristics table indicates that an

MMBF4392 has an I DSS range of 25 to 75 mA. Figure

10 shows r DS(on) = 52 W for I DSS = 25 mA and 30 W for

I DSS = 75 mA. The corresponding V GS values are 2.2 V

and 4.8 V.

(6)

SOT−23 (TO−236) CASE 318−08

ISSUE AS

DATE 30 JAN 2018 SCALE 4:1

D

A1

3

1 2

1

XXXMG G

XXX = Specific Device Code M = Date Code

G = Pb−Free Package

*This information is generic. Please refer to device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “ G”, may or may not be present.

GENERIC MARKING DIAGRAM*

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH.

MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF THE BASE MATERIAL.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS.

SOLDERING FOOTPRINT

VIEW C L

0.25

e L1

E E

b

A

SEE VIEW C

DIM

A MIN NOM MAX MIN

MILLIMETERS

0.89 1.00 1.11 0.035 INCHES

A1 0.01 0.06 0.10 0.000

b 0.37 0.44 0.50 0.015

c 0.08 0.14 0.20 0.003

D 2.80 2.90 3.04 0.110

E 1.20 1.30 1.40 0.047

e 1.78 1.90 2.04 0.070

L 0.30 0.43 0.55 0.012

0.039 0.044 0.002 0.004 0.017 0.020 0.006 0.008 0.114 0.120 0.051 0.055 0.075 0.080 0.017 0.022 NOM MAX

L1

H

STYLE 22:

PIN 1. RETURN 2. OUTPUT 3. INPUT STYLE 6:

PIN 1. BASE 2. EMITTER 3. COLLECTOR

STYLE 7:

PIN 1. EMITTER 2. BASE 3. COLLECTOR

STYLE 8:

PIN 1. ANODE 2. NO CONNECTION 3. CATHODE STYLE 9:

PIN 1. ANODE 2. ANODE 3. CATHODE

STYLE 10:

PIN 1. DRAIN 2. SOURCE 3. GATE

STYLE 11:

PIN 1. ANODE 2. CATHODE 3. CATHODE−ANODE

STYLE 12:

PIN 1. CATHODE 2. CATHODE 3. ANODE

STYLE 13:

PIN 1. SOURCE 2. DRAIN 3. GATE

STYLE 14:

PIN 1. CATHODE 2. GATE 3. ANODE STYLE 15:

PIN 1. GATE 2. CATHODE 3. ANODE

STYLE 16:

PIN 1. ANODE 2. CATHODE 3. CATHODE

STYLE 17:

PIN 1. NO CONNECTION 2. ANODE 3. CATHODE

STYLE 18:

PIN 1. NO CONNECTION 2. CATHODE 3. ANODE

STYLE 19:

PIN 1. CATHODE 2. ANODE 3. CATHODE−ANODE STYLE 23:

PIN 1. ANODE 2. ANODE 3. CATHODE

STYLE 20:

PIN 1. CATHODE 2. ANODE 3. GATE STYLE 21:

PIN 1. GATE 2. SOURCE 3. DRAIN STYLE 1 THRU 5:

CANCELLED

STYLE 24:

PIN 1. GATE 2. DRAIN 3. SOURCE

STYLE 25:

PIN 1. ANODE 2. CATHODE 3. GATE

STYLE 26:

PIN 1. CATHODE 2. ANODE 3. NO CONNECTION STYLE 27:

PIN 1. CATHODE 2. CATHODE 3. CATHODE

2.10 2.40 2.64 0.083 0.094 0.104 HE

0.35 0.54 0.69 0.014 0.021 0.027

c

T 0° −−− 10° 0° −−− 10°

T

3X

TOP VIEW

SIDE VIEW

END VIEW

2.90

0.80

DIMENSIONS: MILLIMETERS

0.90

PITCH

3X

3X

0.95

RECOMMENDED

STYLE 28:

PIN 1. ANODE 2. ANODE 3. ANODE

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others.

98ASB42226B DOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 1 SOT−23 (TO−236)

© Semiconductor Components Industries, LLC, 2019

www.onsemi.com

(7)

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information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of

information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of

information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of

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information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of