MOSFET – Dual N-Channel, POWERTRENCH®

MOSFET – Dual N-Channel, POWERTRENCH ^®

20V, 1.2A, 175mW

FDG1024NZ

Description

This dual N−Channel logic level enhancement mode field effect transistors are produced using onsemi’s proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on−state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETs. Since bias resistors are not required, this dual digital FET can replace several different digital transistors, with different bias resistor values.

Features

• ^{Max r}

= 175 m W at V

= 4.5 V, I

= 1.2 A

• ^{Max r}

= 215 m W at V

= 2.5 V, I

= 1.0 A

• ^{Max r}

= 270 m W at V

= 1.8 V, I

= 0.9 A

• ^{Max r}

= 389 m W at V

= 1.5 V, I

= 0.8 A

• HBM ESD Protection Level > 2 kV (Note 3)

• Very Low Level Gate Drive Requirements Allowing Operation in 1.5 V Circuits (V

) < 1 V)

• Very Small Package Outline SC−88/SC−70 6 Lead

• RoHS Compliant

• These Device is Halogen Free

MOSFET MAXIMUM RATINGS (T_A = 25°C unless otherwise noted)

Symbol Parameter Ratings Unit

VDS Drain to Source Voltage 20 V

VGS Gate to Source Voltage ±8 V

ID Drain Current Continuous TA = 25°C

(Note 1a) 1.2 A

Pulsed 6

P_D Power

Dissipation T_A = 25°C (Note 1a) 0.36 W T_A = 25°C (Note 1b) 0.30

T_J, T_STG Operating and Storage Junction

Temperature Range −55 to +150 °C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

ORDERING INFORMATION See detailed ordering and shipping information on page 3 of this data sheet.

MARKING DIAGRAM SC−88/SC−70 6 Lead, 1.25 x 2

CASE 419AD

&E&E&E

&Y

&.4N&G

&E = Designates Space

&Y = Binary Calendar Year

&.4N = Specific Device Code

&G = 1−Digit Weekly Date Code Pin 1

ELECTRICAL CONNECTION S1

G1D2 D1G2S2

S1

G1

D2

D1

G2

3 or 6 S2 2 or 5 1 or 4*

4 or 1*

5 or 2 6 or 3

* The pinouts are symmetrical; pin 1 and 4 are interchangeable.

Units inside the carrier can be of either orientation and will not affect the functionality of the device.

N−Channel MOSFET

THERMAL CHARACTERISTICS

Symbol Parameter Ratings Unit

R_qJA Thermal Resistance, Junction to Ambient (Note 1a) 350 _C/W

R_qJA Thermal Resistance, Junction to Ambient (Note 1b) 415

ELECTRICAL CHARACTERISTICS (T_J = 25°C unless otherwise noted)

Symbol Parameter Test Conditions Min. Typ. Max. Unit

OFF CHARACTERISTICS

BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V 20 − − V

DBV_DSS DT_J

Breakdown Voltage Temperature

Coefficient I_D = 250 μA, referenced to 25°C − 14 − mV/°C

I_DSS Zero Gate Voltage Drain Current V_DS = 16 V, V_GS = 0 V − − 1 μA

I_GSS Gate to Source Leakage Current V_GS = ±8 V, VDS = 0 V − − ±10 μA

ON CHARACTERISTICS

V_GS(th) Gate to Source Threshold Voltage V_GS = V_DS, ID = 250 μA 0.4 0.8 1.0 V DV_GS(th)

DTJ

Gate to Source Threshold Voltage

Temperature Coefficient I_D = 250 μA, referenced to 25°C − −3 − mV/°C

rDS(ON) Static Drain to Source On Resistance V_GS = 4.5 V, I_D = 1.2 A − 160 175 mΩ

V_GS = 2.5 V, I_D = 1.0 A − 185 215

V_GS = 1.8 V, I_D = 0.9 A − 232 270

VGS = 1.5 V, ID = 0.8 A − 321 389

V_GS = 4.5 V, I_D = 1.2 A, T_J = 125°C − 220 259

g_FS Forward Transconductance V_DD = 5 V, I_D = 1.2 A − 4 − S

DYNAMIC CHARACTERISTICS

C_iSS Input Capacitance V_DS = 10 V, V_GS = 0 V, f = 1 MHz

− 115 150 pF

C_OSS Output Capacitance − 25 35 pF

Crss Reverse Transfer Capacitance − 20 25 pF

R_g Gate Resistance − 4.6 − Ω

SWITCHING CHARACTERISTICS

t_d(on) Turn−On Delay Time VDD = 10 V, ID = 1.2 A,

V_GS = 4.5 V, R_GEN = 6 Ω − 3.7 10 ns

t_r Rise Time − 1.7 10 ns

t_d(off) Turn−Off Delay Time − 11 19 ns

tf Fall Time − 1.5 10 ns

Q_g Total Gate Charge V_GS = 4.5 V, V_DD = 10 V, I_D = 1.2 A − 1.8 2.6 nC

Qgs Gate to Source Charge − 0.3 − nC

Qgd Gate to Drain “Miller” Charge − 0.4 − nC

DRAIN−SOURCE DIODE CHARACTERISTICS

IS Maximum Continuous Drain−Source Diode Forward Current − − 0.3 A

V_SD Source to Drain Diode Forward

Voltage V_GS = 0 V, I_S = 0.3 A (Note 2) − 0.7 1.2 V

t_rr Reverse Recovery Time I_F = 1.2 A, di/dt = 100 A/ms − 10 20 ns

Qrr Reverse Recovery Charge − 1.9 10 nC

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

NOTES:

1. R_qJA is determined with the device mounted on a 1 in² pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR−4 material. R_qJC is guaranteed by design while R_θJA is determined by the user’s board design.

a. 350°C/W when mounted

on a 1 in² pad of 2 oz copper b. 415°C/W when mounted on

a minimum pad of 2 oz copper

2. Pulse Test: Pulse Width < 300ms, Duty cycle < 2.0%.

3. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.

PACKAGE MARKING AND ORDERING INFORMATION

ORDERING INFORMATION

Device Marking Device Package Reel Size Tape Width Shipping^†

.4N FDG1024NZ SC−88/SC−70 6 Lead

(Halogen Free) 7" 8 mm 3000 / Tape and Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.

TYPICAL CHARACTERISTICS

(T_J = 25°C unless otherwise noted)

0 1 2 3 4

0 1 2 3 4 5 6

1.0 1.5 2.0 2.5 3.0 3.5

Figure 1. On−Region Characteristics Figure 2. Normalized On−Resistance vs.

Drain Current and Gate Voltage

Figure 3. Normalized On−Resistance vs.

Junction Temperature Figure 4. On−Resistance vs. Gate to Source Voltage

Figure 5. Transfer Characteristics Figure 6. Source to Drain Diode V_DS, Drain to Source Voltage (V)

ID, Drain Current (A)

0 1 2 3 4 5

0 0.4 0.8 1.2 1.6 2.0

VGS = 2.5 V

Pulse Duration = 80 ms Duty Cycle = 0.5% Max

I_D, Drain Current (A) Normalized Drain to Source On−Resistance

0 1 2 3 4 5

0.5 1.0 1.5 2.0 2.5

V_GS = 1.5 V

Pulse Duration = 80 ms Duty Cycle = 0.5% Max

T_J, Junction Temperature (5C) Normalized Drain to Source On−Resistance

0.6−75 0.8 1.0 1.2 1.4 1.6

−50 −25 0 25 50 75 100 125 150

I_D = 1.2 A V_GS = 4.5 V

V_GS, Gate to Source Voltage (V) rDS(on), Drain to Source On−Resistance (mW)

0 100 200 300 400 500

V_GS, Gate to Source Voltage (V) ID, Drain Current (A)

Pulse Duration = 80 ms Duty Cycle = 0.5% Max V_DS = 5 V

T_J = 125°C

T_J = 25°C

T_J = −55°C

V_SD, Body Diode Forward Voltage (V) IS, Reverse Drain Current (A)

0.2 0.4 0.6 0.8 1.0 1.2 1.4

0.01 0.1 1

10 V_GS = 0 V

TJ = 125°C

T_J = 25°C

TJ = −55°C T_J = 125°C

T_J = 25°C Pulse Duration = 80 ms Duty Cycle = 0.5% Max

I_D = 1.2 A 6

6 VGS = 1.8 V

V_GS = 1.5 V V_GS = 4.5 V

V_GS = 3.5 V V_GS = 1.8 V

V_GS = 2.5 V

V_GS = 3.5 V

V_GS = 4.5 V

600

4.0 4.5

TYPICAL CHARACTERISTICS

Ig, Gate Leakage Current (mA) 10⁻³ 10⁻¹ 10 10³

10⁻¹

Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs.

Drain to Source Voltage

Figure 9. Forward Bias Safe Operating Area Figure 10. Gate Leakage Current vs.

Gate to Source Voltage Q_g, Gate Charge (nC)

VGS, Gate to Source Voltage (V) 0

0

V_DD = 15 V

0.5 1.0 1.5 2.0 2.5

1 2 3 4

5 ID = 1.2 A

VDD = 10 V VDD = 5 V

0.1

V_DS, Drain to Source Voltage (V)

Capacitance (pF)

5 1 10 20

10 100 300

f = 1 MHz V_GS = 0 V

C_iss

C_oss

Crss

V_DS, Drain to Source Voltage (V) ID, Drain Current (A)

0.010.01 0.1

1 10

0.1 1 10 100

10 ms

100 ms 1 s DC This Area is

Limited by r_DS(on)

Single Pulse T_J = Max Rated R_qJA = 415°C/W TA = 25°C

V_GS, Gate to Source Voltage (V)

0 2 4 6 8 10

Single Pulse R_qJA = 415°C/W T_A = 25°C V_GS = 4.5 V

0.1 1 10 100

10⁻⁴ 10⁻³ 10⁻² 1 10 100 1000

1 ms 0.1 ms

10⁵

12 14

V_GS = 0 V

T_J = 125°C

T_J = 25°C

P(PK), Peak Transient Power (W)

TYPICAL CHARACTERISTICS

Figure 12. Transient Thermal Response Curve t, Rectangular Pulse Duration (s)

10⁻⁴ 10⁻³ 10⁻² 10⁻¹ 1 10

Single Pulse R_qJA = 415°C D = 0.5

0.2 0.1 0.05 0.02 0.01

Duty Cycle−Descending Order

0.01 0.1 1 2

0.001

100 1000

PDM

t₁ t₂ Notes:

Duty Factor: D = t₁/t₂

Peak T_J = P_DM x Z_qJA x R_qJA + T_A Normalized Thermal Impedance, ZqJA

SC−88 (SC−70 6 Lead), 1.25x2 CASE 419AD

ISSUE A

DATE 07 JUL 2010

E1 D

A

L

L1 L2

e e

b

A1 A2

c TOP VIEW

SIDE VIEW END VIEW

q1

q1

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MO-203.

E

q

SYMBOL MIN NOM MAX

θ A A1

b c D E E1

e L

0º 8º

L2

0.00

0.15 0.10

0.26 1.80 1.80 1.15

0.65 BSC

0.15 BSC

1.10 0.10

0.30 0.18

0.46 2.20 2.40 1.35

L1

0.80

θ1 4º 10º

A2 0.80 1.00

0.42 REF 0.36 2.00 2.10 1.25 1

98AON34266E DOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 1 OF 1 SC−88 (SC−70 6 LEAD), 1.25X2

information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION