FDMC8010 MOSFET – N-Channel, POWERTRENCH

MOSFET – N-Channel, POWERTRENCH ⁾

30 V, 75 A, 1.3 mW

General Description

This N−Channel MOSFET is produced using ON Semiconductor’s advanced POWERTRENCH process that has been especially tailored to minimize the on−state resistance. This device is well suited for applications where ultra low r

is required in small spaces such as High performance VRM, POL and Oring functions.

Features

• ^{Max r}

= 1.3 m W at V

= 10 V, I

= 30 A

• Max r

= 1.8 mW at V

= 4.5 V, I

= 25 A

• High Performance Technology for Extremely Low r

• These Devices are Pb−Free and are RoHS Compliant

• DC − DC Buck Converters

• Point of Load

• High Efficiency Load Switch and Low Side Switching

• ^{Oring FET}

MOSFET MAXIMUM RATINGS (T_A = 25°C Unless Otherwise Noted)

Symbol Parameter Ratings Units

V^DS Drain to Source Voltage 30 V

VGS Gate to Source Volage (Note 4) ±20 V

ID Drain Current

−Continuous (Package limited) TC = 25°C

−Continuous (Silicon limited) TC = 25°C

−Continuous TA = 25°C (Note 1a)

−Pulsed

16675 12030

A

EAS Single Pulse Avalance Energy (Note 3) 153 mJ

PD Power Dissipation TC = 25°C 54 W

Power Dissipation TA = 25°C (Note 1a) 2.4 TJ, TSTG Operating and Storage Junction Temperature

Range −55 to

+150 °C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

THERMAL CHARACTERISTICS

Symbol Parameter Ratings Unit

RθJC Thermal Resistance, Junction to Case 1.3 °C/W RθJA Thermal Resistance, Junction to Ambient 53 °C/W

www.onsemi.com

PQFN8 3.3x3.3, 0.65P CASE 483AW

Power 33

MARKING DIAGRAM

See detailed ordering, marking and shipping information in the package dimensions section on page 2 of this data sheet.

ORDERING INFORMATION

Bottom Top

Pin 1 Pin 1

G

D

SS S

DD D

$Y&Z&3&K FDMC 8010

S S S G

D D D D

$Y = ON Semiconductor Logo

&Z = Assembly Plant Code

&3 = Numeric Date Code

&K = Lot Code

FDMC8010 = Specific Device Code

PACKAGE MARKING AND ORDERING INFORMATION

Device Marking Device Package Reel Size Tape Width Quantity

FDMC8010 FDMC8010 Power 33 13” 12 mm 3000 Units

ELECTRICAL CHARACTERISTICS(T_J = 25°C unless otherwise noted)

Symbol Parameter Test Condition Min Typ Max Unit

OFF CHARACTERISTICS

BV_DSS Drain to Source Breakdown Voltage I_D = 1 mA, V_GS = 0 V 30 V

DBV_DSS/DT_J Breakdown Voltage Temperature Coef-

ficient ID = 1 mA, referenced to 25°C 15 mV/°C

I_DSS Zero Gate Voltage Drain Current V_DS = 24 V, V_GS = 0 V 1 mA

I_GSS Gate to Source Leakage Current V_GS = 20 V, V_DS = 0 V 100 nA

ON CHARACTERISTICS

V_GS(th) Gate to Source Threshold Voltage V_GS = V_DS, I_D = 1 mA 1.2 1.5 2.5 V

DV_GS(th)/DT_J Gate to Source Threshold Voltage Tem-

perature Coefficient I_D = 1 mA, referenced to 25°C −5 mV/°C

r_DS(on) Static Drain to Source On Resistance V_GS = 10 V, I_D = 30 A 0.9 1.3 mW

V_GS = 4.5 V, I_D = 25 A 1.3 1.8

V_GS = 10 V, I_D = 30 A, T_J = 125°C 1.3 2

g_FS Forward Transconductance V_DS = 5 V, I_D = 30 A 188 S

DYNAMIC CHARACTERISTICS

C_iss Input Capacitance V_DS = 15 V, V_GS = 0 V, f = 1 MHz

4405 5860 pF

Coss Output Capacitance 1570 2090 pF

C_rss Reverse Transfer Capacitance 167 250 pF

Rg Gate Resistance 0.1 0.5 1.25 W

SWITCHING CHARACTERISTICS

t_d(on) Turn−On Delay Time V_DD = 15 V, I_D = 30 A, V_GS = 10 V,

R_GEN = 6 W 15 27 ns

tr Rise Time 7.5 15 ns

t_d(off) Turn−Off Delay Time 40 64 ns

tf Fall Time 5.3 11 ns

Q_g Total Gate Charge V_GS = 0 V to 10 V V_DD = 15 V

ID = 30 A 67 94 nC

Q_g Total Gate Charge V_GS = 0 V to 4.5 V 32 45 nC

Qgs Gate to Source Charge 10 nC

Qgd Gate to Drain “Miller” Charge 9.5 nC

DRAIN−SOURCE DIODE CHARACTERISTICS

VSD Source to Drain Diode Forward Voltage V_GS = 0 V, I_S = 2 A (Note 2) 0.6 1.2 V V_GS = 0 V, I_S = 30 A (Note 2) 0.7 1.2

t_rr Reverse Recovery Time I_F = 30 A, di/dt = 100 A/ms 49 78 ns

Q_rr Reverse Recovery Charge 29 46 nC

NOTES:

1. R_θJA is determined with the device mounted on a 1 in² pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR−4 material. R_θJC is guaranteed by design while R_θCA is determined by the user’s board design.

a. 53 °C/W when mounted on a

1 in²pad of 2 oz copper. b. 125 °C/W when mounted on a minimum pad of 2 oz copper.

G DF DS SF SS G DF DS SF SS

2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0 %.

3. E_AS of 153 mJ is based on starting T_J = 25 °C, L = 0.3 mH, IAS = 32 A, V_DD = 27 V, V_GS = 10 V. 100% test at L = 0.1 mH, I_AS = 47 A.

4. As an N−ch device, the negative Vgs rating is for low duty cycle pulse occurrence only. No continuous rating is implied.

TYPICAL CHARACTERISTICS

T_J = 25°C Unless Otherwise Noted

Figure 1. On−Region Characteristics Figure 2. Noormalized On−Resistance vs Drain Current and Gate Voltage

Figure 3. Normalized On Resistance vs Junction Temperature

Figure 4. On−Resistance vs Gate to Source Voltage

V_DS, DRAIN−TO−SOURCE VOLTAGE (V)

NORMALIZED DRAIN TO SOURCE ON−RESISTANCE

TJ, JUNCTION TEMPERATURE (°C)

rDS(ON), DRAIN−TO−SOURCE ON−RESISTANCE (mW)

ID, DRAIN CURRENT (A) IS, REVERSE DRAIN CURRENT (A)

0.0 0.2 0.4 0.6

0 40 80 120

PULSE DURATION = 80ms DUTY CYCLE = 0.5% MAX

PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX

−75 −50 −25 0 25 50 75 100 125 150 0.6

0.8 1.0 1.2 1.4 1.6

PULSE DURATION = 80ms DUTY CYCLE = 0.5% MAX

1.0 1.5 2.0 2.5 3.0

0 40 80 120

PULSE DURATION = 80ms DUTY CYCLE = 0.5% MAX

0.0 0.2 0.4 0.6 0.8 1.0 1.2

0.001 0.01 0.1 1 10 100200

I_D, DRAIN CURRENT (A) ID, DRAIN CURRENT (A)NORMALIZED DRAIN TO SOURCE ON−RESISTANCE

VGS, GATE TO SOURCE VOLTAGE (V)

V_GS, GATE TO SOURCE VOLTAGE (V) V_SD, BODY DIODE FORWARD VOLTAGE (V) 5

4 3 2 1

0

0 40 80 120

V_GS = 10 V V_GS = 4.5 V V_GS = 4 V V_GS = 3.5 V

V_GS = 3 V

V_GS = 3 V

V_GS = 3.5 V

V_GS = 4 V

V_GS = 4.5 V V_GS = 10 V

ID = 30 A V_GS = 10 V

I_D = 30 A

TJ = 125°C

T_J = 25°C

T_J = 150°C V_DS = 5 V

T_J = 25°C

T_J = −55°C

V_GS = 0 V

T_J = 150°C

T_J = 25°C

T_J = −55°C 5

4 3 2 1

0 2 4 6 8 10

TYPICAL CHARACTERISTICS

Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain to Source Voltage

Figure 9. Unclamped Inductive Switching Capability

Figure 10. Maximum Continuous Drain Current vs Case Temperature Q_g, GATE CHARGE (nC)

CAPACITANCE (pF)

tAV, TIME IN AVALANCHE (ms)

ID, DRAIN CURRENT (A)

ID, DRAIN CURRENT (A) P(PK), PEAK TRANSIENT POWER (W)

V_DS, DRAIN TO SOURCE VOLTAGE (V) VGS, GATE TO SOURCE VOLTAGE (V)IAS, AVALANCHE CURRENT (A)

TC, CASE TEMPERATURE (°C)

ID= 30 A

VDD = 18 V VDD= 12 V

VDD = 15 V

0.1 1 10 30

100 1000 10000

f = 1 MHz VGS = 0 V

Crss Coss Ciss

0.0011 0.01 0.1 1 10 100 500

10 100

25 50 75 100 125 150

0 50 100 150 200

Limited by Package VGS= 4.5 V

VGS= 10 V

0.01 0.1 1 10 100200

0.01 0.1 1 10 100 200

100ms

10 ms

10 s 100 ms

DC 1 s 1 ms THIS AREA IS

LIMITED BY rDS(on) SINGLE PULSE TJ= MAX RATED

10⁻⁴ 10⁻³ 10⁻² 10⁻¹ 1 10 100 1000 0.5

1 10 100 1000 3000

SINGLE PULSE R_qJA = 125°C/W

0 20 40 60 80

0 2 4 6 8 10

T_A = 25°C

R_qJA = 125°C/W TA = 25°C

T_J = 125°C

T_J = 100°C TJ = 25°C

R_qJA = 2.3°C/W

TYPICAL CHARACTERISTICS

Figure 13. Junction−to−Ambient Transient Thermal Response Curve NORMALIZED THERMAL IMPEDANCE, ZqJA

t, RECTANGULAR PULSE DURATION (sec)

10⁻⁴ 10⁻³ 10⁻² 10⁻¹ 11 0 100 1000

0.0001 0.001 0.01 0.1 1 2

D = 0.5 0.2 0.1 0.05 0.02 0.01

SINGLE PULSE R_qJA = 125°C/W DUTY CYCLE−DESCENDING ORDER

P_DM

t₁ t₂ NOTES:

DUTY FACTOR: D = t1/t₂ PEAK T_J = P_DM x Z_qJA x R_qJA + T_A

WDFN8 3.3X3.3, 0.65P CASE 483AW

ISSUE A

DATE 10 SEP 2019

XXXX = Specific Device Code A = Assembly Location Y = Year

WW = Work Week

*This information is generic. Please refer to device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking.

GENERIC MARKING DIAGRAM*

XXXX AYWW

98AON13672G

DOCUMENT NUMBER: Electronic versions are uncontrolled except when accessed directly from the Document Repository.

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