Asynchronous Counter Mode
REGISTER 13-2: TxGCON: TIMER1/3 GATE CONTROL REGISTER
R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x R/W-0/u R/W-0/u
TMRxGE TxGPOL TxGTM TxGSPM TxGGO/DONE TxGVAL TxGSS<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 TMRxGE: Timer1/3 Gate Enable bit
If TMRxON = 0:
This bit is ignored If TMRxON = 1:
1 = Timer1/3 counting is controlled by the Timer1/3 gate function 0 = Timer1/3 counts regardless of Timer1/3 gate function bit 6 TxGPOL: Timer1/3 Gate Polarity bit
1 = Timer1/3 gate is active-high (Timer1/3 counts when gate is high) 0 = Timer1/3 gate is active-low (Timer1/3 counts when gate is low) bit 5 TxGTM: Timer1/3 Gate Toggle Mode bit
1 = Timer1/3 Gate Toggle mode is enabled
0 = Timer1/3 Gate Toggle mode is disabled and toggle flip-flop is cleared Timer1/3 gate flip-flop toggles on every rising edge.
bit 4 TxGSPM: Timer1/3 Gate Single-Pulse Mode bit
1 = Timer1/3 gate Single-Pulse mode is enabled and is controlling Timer1/3 gate 0 = Timer1/3 gate Single-Pulse mode is disabled
bit 3 TxGGO/DONE: Timer1/3 Gate Single-Pulse Acquisition Status bit 1 = Timer1/3 gate single-pulse acquisition is ready, waiting for an edge
0 = Timer1/3 gate single-pulse acquisition has completed or has not been started This bit is automatically cleared when TxGSPM is cleared.
bit 2 TxGVAL: Timer1/3 Gate Current State bit
Indicates the current state of the Timer1/3 gate that could be provided to TMRxH:TMRxL.
Unaffected by Timer1/3 Gate Enable (TMRxGE).
bit 1-0 TxGSS<1:0>: Timer1/3 Gate Source Select bits 00 = Timer1/3 Gate pin
01 = Timer2 Match PR2 output
10 = Comparator 1 optionally synchronized output (sync_C1OUT) 11 = Comparator 2 optionally synchronized output (sync_C2OUT)
PIC18(L)F2X/45K50
TABLE 13-5: REGISTERS ASSOCIATED WITH TIMER1/3 AS A TIMER/COUNTER
TABLE 13-6: CONFIGURATION REGISTERS ASSOCIATED WITH TIMER1/3
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on page
ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 148
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114
IPR1 ACTIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 123
IPR2 OSCFIP C1IP C2IP EEIP BCLIP HLVDIP TMR3IP CCP2IP 124
IPR3 — — — — CTMUIP USBIP TMR3GIP TMR1GIP 125
PIE1 ACTIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 120
PIE2 OSCFIE C1IE C2IE EEIE BCLIE HLVDIE TMR3IE CCP2IE 121
PIE3 — — — — CTMUIE USBIE TMR3GIE TMR1GIE 122
PIR1 ACTIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 117
PIR2 OSCFIF C1IF C2IF EEIF BCLIF HLVDIF TMR3IF CCP2IF 118
PIR3 — — — — CTMUIF USBIF TMR3GIF TMR1GIF 119
PMD0 — UARTMD USBMD ACTMD — TMR3MD TMR2MD TMR1MD 61
T1CON TMR1CS<1:0> T1CKPS<1:0> SOSCEN T1SYNC RD16 TMR1ON 165
T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 166
T3CON TMR3CS<1:0> T3CKPS<1:0> SOSCEN T3SYNC RD16 TMR3ON 165
T3GCON TMR3GE T3GPOL T3GTM T3GSPM T3GGO/DONE T3GVAL T3GSS<1:0> 166
TMRxH Timer1/3 Register, High Byte —
TMRxL Timer1/3 Register, Low Byte —
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 149
TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 149
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on page
CONFIG3H MCLRE SDOMX — T3CMX — — PBADEN CCP2MX 376
PIC18(L)F2X/45K50
14.0 TIMER2 MODULE
The Timer2 module incorporates the following features:
• 8-bit Timer and Period registers (TMR2 and PR2, respectively)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 match with PR2, respectively
• Optional use as the shift clock for the MSSP module
See Figure 14-1 for a block diagram of Timer2.
FIGURE 14-1: TIMER2 BLOCK DIAGRAM
Comparator
TMRx Sets Flag
TMRx
Output
Reset
Postscaler Prescaler
PRx 2
FOSC/4
1:1 to 1:16 1:1, 1:4, 1:16
EQ
4
bit TMRxIF
TxOUTPS<3:0>
TxCKPS<1:0>
PIC18(L)F2X/45K50
14.1 Timer2 Operation
The clock input to the Timer2 module is the system instruction clock (FOSC/4).
TMR2 increments from 00h on each clock edge.
A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options.
These options are selected by the prescaler control bits, T2CKPS<1:0> of the T2CON register. The value of TMR2 is compared to that of the Period register, PR2, on each clock cycle. When the two values match, the comparator generates a match signal as the timer output. This signal also resets the value of TMR2 to 00h on the next cycle and drives the output counter/postscaler (see Section 14.2 “Timer2 Interrupt”).
The TMR2 and PR2 registers are both directly readable and writable. The TMR2 register is cleared on any device Reset, whereas the PR2 register initializes to FFh. Both the prescaler and postscaler counters are cleared on the following events:
• a write to the TMR2 register
• a write to the T2CON register
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• MCLR Reset
• Watchdog Timer (WDT) Reset
• Stack Overflow Reset
• Stack Underflow Reset
• RESET Instruction
14.2 Timer2 Interrupt
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (TMR2-to-PR2 match) provides the input for the 4-bit counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF of the PIR1 register. The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE of the PIE1 register. Interrupt Priority is selected with the TMR2IP bit in the IPR1 register.
A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS<3:0>, of the T2CON register.
14.3 Timer2 Output
The unscaled output of TMR2 is available primarily to the CCP modules, where it is used as a time base for operations in PWM mode.
Timer2 can be optionally used as the shift clock source for the MSSP module operating in SPI mode by setting SSPM<3:0> = 0011 in the SSPxCON1 register.
Additional information is provided in Section 16.0
“Master Synchronous Serial Port (MSSP) Module”.
14.4 Timer2 Operation During Sleep
The Timer2 timers cannot be operated while the processor is in Sleep mode. The contents of the TMR2 and PR2 registers will remain unchanged while the processor is in Sleep mode.
14.5 Peripheral Module Disable
When a peripheral module is not used or inactive, the module can be disabled by setting the Module Disable bit in the PMD registers. This will reduce power con-sumption to an absolute minimum. Setting the PMD bits holds the module in Reset and disconnects the module’s clock source. The Module Disable bit for Tim-er2 (TMR2MD) is in the PMD0 register. See Section 4.0 “Power-Managed Modes” for more information.
Note: TMR2 is not cleared when T2CON is written.