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Additional PORTB Pin Functions

ドキュメント内 pic18f45k50unlocked (ページ 133-137)

REGISTER 10-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3

11.3 Additional PORTB Pin Functions

PIC18(L)F2X/45K50

PIC18(L)F2X/45K50

A mismatch condition will continue to set the IOCIF flag bit. Reading or writing PORTB will end the mismatch condition and allow the IOCIF bit to be cleared. The latch holding the last read value is not affected by a MCLR nor Brown-out Reset. After either one of these Resets, the IOCIF flag will continue to be set if a mismatch is present.

The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature.

11.3.3 ALTERNATE FUNCTIONS

PORTB is multiplexed with several peripheral functions (Table 11-5). The pins have TTL input buffers. Some of these pin functions can be relocated to alternate pins using the Control fuse bits in CONFIG3H. RB3 is the default pin for SDO. Clearing the SDOMX bit moves the SDO pin function to RC7.

Two other pin functions, T3CKI and CCP2, can be relocated from their default pins to PORTB pins by clearing the control fuses in CONFIG3H. Clearing T3CMX and CCP2MX moves the pin functions to RB5 and RB3, respectively.

Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the IOCIF interrupt flag may not get set. Furthermore, since a read or write on a port affects all bits of that port, care must be taken when using multiple pins in Interrupt-on-Change mode. Changes on one pin may not be seen while servicing changes on another pin.

TABLE 11-5: PORTB I/O SUMMARY

Pin Function TRIS

Setting

ANSEL Setting

Pin Type

Buffer

Type Description

RB0/INT0/FLT0/

SRI/SDA/SDI/AN12

RB0 0 x O DIG LATB<0> data output; not affected by analog input.

1 0 I TTL PORTB<0> data input; disabled when analog input enabled.

INT0 1 0 I ST External interrupt 0.

FLT0 1 0 I ST PWM Fault input for ECCP auto-shutdown.

SRI 1 0 I ST SR latch input.

SDA 1 0 I/O I2C™ I2C Data I/O (MSSP).

SDI 1 0 I ST SPI Data in (MSSP).

AN12 1 1 I AN Analog input 12.

RB1/INT1/P1C/

SCK/SCL/C12IN3-/

AN10

RB1 0 x O DIG LATB<1> data output; not affected by analog input.

1 0 I TTL PORTB<1> data input; disabled when analog input enabled.

INT1 1 0 I ST External Interrupt 1.

P1C(3) 0 0 O DIG Enhanced CCP1 PWM output 3.

SCK 0 0 O DIG MSSP SPI Clock output.

1 0 I ST MSSP SPI Clock input.

SCL 0 0 O DIG MSSP I2C Clock output.

1 0 I I2C MSSP I2C Clock input.

C12IN3- 1 1 I AN Comparators C1 and C2 inverting input.

AN10 1 1 I AN Analog input 10.

Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal;

CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C = Schmitt Trigger input with I2C.

Note 1: Default pin assignment for SDO when Configuration bit SDOMX is set.

2: Alternate pin assignment for T3CKI and CCP2 when Configuration bits T3CMX and CCP2MX are clear.

3: Function is on PORTD/PORTE for PIC18(L)F45K50 devices.

PIC18(L)F2X/45K50

RB2/INT2/CTED1/

P1B/AN8

RB2 0 x O DIG LATB<2> data output; not affected by analog input.

1 0 I TTL PORTB<2> data input; disabled when analog input enabled.

INT2 1 0 I ST External interrupt 2.

CTED1 1 0 I ST CTMU Edge 1 input.

P1B(3) 0 0 O DIG Enhanced CCP1 PWM output 2.

AN8 1 1 I AN Analog input 8.

RB3/CTED2/CCP2/

SDO/C12IN2-/AN9

RB3 0 x O DIG LATB<3> data output; not affected by analog input.

1 0 I TTL PORTB<3> data input; disabled when analog input enabled.

CTED2 1 0 I ST CTMU Edge 2 input.

CCP2(2) 0 0 O DIG Compare 2 output/PWM 2 output.

1 0 I ST Capture 2 input.

SDO(1) 0 0 O DIG MSSP SPI data output.

C12IN2- 1 1 I AN Comparators C1 and C2 inverting input.

AN9 1 1 I AN Analog input 9.

RB4/IOCB4/P1D/

AN11

RB4 0 x O DIG LATB<4> data output; not affected by analog input.

1 0 I TTL PORTB<4> data input; disabled when analog input enabled.

IOCB4 1 0 I TTL Interrupt-on-change pin.

P1D(3) 0 0 O DIG Enhanced CCP1 PWM output 4.

AN11 1 1 I AN Analog input 11.

RB5/IOCB5/T3CKI/

T1G/AN13

RB5 0 x O DIG LATB<5> data output; not affected by analog input.

1 0 I TTL PORTB<5> data input; disabled when analog input enabled.

IOCB5 1 0 I TTL Interrupt-on-change pin 1.

T3CKI(2) 1 0 I ST Timer3 clock input.

T1G 1 0 I ST Timer1 external clock gate input.

AN13 1 1 I AN Analog input 13.

RB6/IOCB6/PGC RB6 0 O DIG LATB<6> data output; not affected by analog input.

1 I TTL PORTB<6> data input; disabled when analog input enabled.

IOCB6 1 I TTL Interrupt-on-change pin.

PGC x I ST In-Circuit Debugger and ICSPTM programming clock input.

RB7/IOCB7/PGD RB7 0 O DIG LATB<7> data output; not affected by analog input.

1 I TTL PORTB<7> data input; disabled when analog input enabled.

IOCB7 1 I TTL Interrupt-on-change pin.

PGD x O DIG In-Circuit Debugger and ICSPTM programming data output.

x I ST In-Circuit Debugger and ICSPTM programming data input.

TABLE 11-5: PORTB I/O SUMMARY (CONTINUED)

Pin Function TRIS

Setting

ANSEL Setting

Pin Type

Buffer

Type Description

Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal;

CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2C = Schmitt Trigger input with I2C.

Note 1: Default pin assignment for SDO when Configuration bit SDOMX is set.

2: Alternate pin assignment for T3CKI and CCP2 when Configuration bits T3CMX and CCP2MX are clear.

3: Function is on PORTD/PORTE for PIC18(L)F45K50 devices.

PIC18(L)F2X/45K50

TABLE 11-6: REGISTERS ASSOCIATED WITH PORTB

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on page

ANSELB ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 148

ECCP1AS ECCP1ASE ECCP1AS<2:0> PSS1AC<1:0> PSS1BD<1:0> 201

CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 197

CCP2CON DC2B<1:0> CCP2M<3:0> 197

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114

INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 TMR0IP IOCIP 115

INTCON3 INT2IP INT1IP INT2IE INT1IE INT2IF INT1IF 116

IOCB IOCB7 IOCB6 IOCB5 IOCB4 151

LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 150

PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 146

SLRCON SLRE(1) SLRD(1) SLRC SLRB SLRA 152

T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 166

T3CON TMR3CS<1:0> T3CKPS<1:0> SOSCEN T3SYNC RD16 TMR3ON 165

TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 149

WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 150

Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTB.

Note 1: Available on PIC18(L)F45K50 devices only.

TABLE 11-7: CONFIGURATION REGISTERS ASSOCIATED WITH PORTB

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register

on page

CONFIG3H MCLRE SDOMX T3CMX PBADEN CCP2MX 376

CONFIG4L DEBUG XINST ICPRT LVP(1) STRVEN 377

Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTB.

Note 1: Can only be changed when in high voltage programming mode.

PIC18(L)F2X/45K50

ドキュメント内 pic18f45k50unlocked (ページ 133-137)