R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TMR0ON T08BIT T0CS T0SE PSA TOPS<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TMR0ON: Timer0 On/Off Control bit
1 = Enables Timer0 0 = Stops Timer0
bit 6 T08BIT: Timer0 8-bit/16-bit Control bit
1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter bit 5 T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (FOSC/4) bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Timer0 Prescaler Assignment bit
1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler.
0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.
bit 2-0 T0PS<2:0>: Timer0 Prescaler Select bits 111 = 1:256 prescale value
110 = 1:128 prescale value 101 = 1:64 prescale value 100 = 1:32 prescale value 011 = 1:16 prescale value 010 = 1:8 prescale value 001 = 1:4 prescale value 000 = 1:2 prescale value
PIC18(L)F2X/45K50
12.2 Timer0 Operation
Timer0 can operate as either a timer or a counter; the mode is selected with the T0CS bit of the T0CON register. In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 12.4
“Prescaler”). Timer0 incrementing is inhibited for two instruction cycles following a TMR0 register write. The user can work around this by adjusting the value written to the TMR0 register to compensate for the anticipated missing increments.
The Counter mode is selected by setting the T0CS bit (= 1). In this mode, Timer0 increments either on every rising or falling edge of pin RA4/T0CKI. The increment-ing edge is determined by the Timer0 Source Edge Select bit, T0SE of the T0CON register; clearing this bit selects the rising edge. Restrictions on the external clock input are discussed below.
An external clock source can be used to drive Timer0;
however, it must meet certain requirements (see Table 29-22) to ensure that the external clock can be synchronized with the internal phase clock (TOSC).
There is a delay between synchronization and the onset of incrementing the timer/counter.
12.3 Timer0 Reads and Writes in 16-Bit Mode
TMR0H is not the actual high byte of Timer0 in 16-bit mode; it is actually a buffered version of the real high byte of Timer0 which is neither directly readable nor writable (refer to Figure 12-2). TMR0H is updated with the contents of the high byte of Timer0 during a read of TMR0L. This provides the ability to read all 16 bits of Timer0 without the need to verify that the read of the high and low byte were valid. Invalid reads could otherwise occur due to a rollover between successive reads of the high and low byte.
Similarly, a write to the high byte of Timer0 must also take place through the TMR0H Buffer register. Writing to TMR0H does not directly affect Timer0. Instead, the high byte of Timer0 is updated with the contents of TMR0H when a write occurs to TMR0L. This allows all 16 bits of Timer0 to be updated at once.
FIGURE 12-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE)
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
T0CKI pin T0SE
0
1
1
0
T0CS FOSC/4
Programmable Prescaler
Sync with Internal
Clocks
TMR0L (2 TCY Delay)
Internal Data Bus PSA
T0PS<2:0>
Set TMR0IF on Overflow
3 8
8
PIC18(L)F2X/45K50
FIGURE 12-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE)
12.4 Prescaler
An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable;
its value is set by the PSA and T0PS<2:0> bits of the T0CON register which determine the prescaler assignment and prescale ratio.
Clearing the PSA bit assigns the prescaler to the Timer0 module. When the prescaler is assigned, prescale values from 1:2 through 1:256 in integer power-of-2 increments are selectable.
When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF TMR0, MOVWF TMR0, BSF TMR0, etc.) clear the prescaler count.
12.4.1 SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software control and can be changed “on-the-fly” during program execution.
12.5 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 reg-ister overflows from FFh to 00h in 8-bit mode, or from FFFFh to 0000h in 16-bit mode. This overflow sets the TMR0IF flag bit. The interrupt can be masked by clear-ing the TMR0IE bit of the INTCON register. Before re-enabling the interrupt, the TMR0IF bit must be cleared by software in the Interrupt Service Routine.
Since Timer0 is shut down in Sleep mode, the TMR0 interrupt cannot awaken the processor from Sleep.
TABLE 12-1: REGISTERS ASSOCIATED WITH TIMER0
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
T0CKI pin T0SE
0
1
1
0
T0CS FOSC/4
Programmable Prescaler
Sync with Internal
Clocks TMR0L
(2 TCY Delay)
Internal Data Bus 8
PSA T0PS<2:0>
Set TMR0IF on Overflow
3
TMR0
TMR0H High Byte
8 8
8
Read TMR0L Write TMR0L
8
Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count but will not change the prescaler assignment.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE IOCIE TMR0IF INT0IF IOCIF 114
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — IOCIP 115
T0CON TMR0ON T08BIT T0CS T0SE PSA T0PS<2:0> 153
TMR0H Timer0 Register, High Byte —
TMR0L Timer0 Register, Low Byte —
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 149
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used by Timer0.
PIC18(L)F2X/45K50
13.0 TIMER1/3 MODULE WITH GATE CONTROL
The Timer1/3 module is a 16-bit timer/counter with the following features:
• 16-bit timer/counter register pair (TMRxH:TMRxL)
• Programmable internal or external clock source
• 2-bit prescaler
• Dedicated Secondary 32 kHz oscillator circuit
• Optionally synchronized comparator out
• Multiple Timer1/3 gate (count enable) sources
• Interrupt on overflow
• Wake-up on overflow (external clock, Asynchronous mode only)
• 16-Bit Read/Write Operation
• Time base for the Capture/Compare function
• Special Event Trigger (with CCP/ECCP)
• Selectable Gate Source Polarity
• Gate Toggle mode
• Gate Single-pulse mode
• Gate Value Status
• Gate Event Interrupt
Figure 13-1 is a block diagram of the Timer1/3 module.
FIGURE 13-1: TIMER1/3 BLOCK DIAGRAM
TMRxH TMRxL
TxSYNC
TxCKPS<1:0>
Prescaler 1, 2, 4, 8
0
1
Synchronized clock input
2 Set flag bit
TMRxIF on
Overflow TMRx(2),(4)
TMRxON
Note 1: ST Buffer is high speed type when using TxCKI.
2: Timer1/3 register increments on rising edge.
3: Synchronize does not operate while in Sleep.
4: See Figure 13-2 for 16-Bit Read/Write Mode Block Diagram.
5: T1CKI is not available when the secondary oscillator is enabled. (SOSCGO = 1 or SOSCEN = 1) 6: T3CKI is not available when the secondary oscillator is enabled, unless T3CMX = 1.
TxG
FOSC/4 Internal Clock SOSCOUT
1
TxCKI 0
TMRxCS<1:0>
(5)
Synchronize(3),(7) det
Sleep input TMRxGE
0
1 00
01
10
11
TxGPOL
D CK Q
Q 0
1
TxGVAL
TxGTM
Single Pulse Acq. Control TxGSPM
TxGGO/DONE TxGSS<1:0>
10 11
00 FOSC 01 Internal Clock Reserved R
D EN
Q Q1
RD TXGCON
Data Bus
det Interrupt
TMRxGIF Set
TxCLK
FOSC/2 Internal Clock D
EN Q TxG_IN
TMRxON Timer2 Match
PR2
sync_C2OUT(7) sync_C1OUT(7)
To Comparator Module
,(6)
SOSCEN Secondary Oscillator Module See Figure 2-4
TxCLK_EXT_SRC (1)
PIC18(L)F2X/45K50
13.1 Timer1/3 Operation
The Timer1/3 module is a 16-bit incrementing counter which is accessed through the TMRxH:TMRxL register pair. Writes to TMRxH or TMRxL directly update the counter.
When used with an internal clock source, the module is a timer and increments on every instruction cycle.
When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source.
Timer1/3 is enabled by configuring the TMRxON and TMRxGE bits in the TxCON and TxGCON registers, respectively. Table 13-1 displays the Timer1/3 enable selections.
13.2 Clock Source Selection
The TMRxCS<1:0> and SOSCEN bits of the TxCON register are used to select the clock source for Timer1/3.
The dedicated secondary oscillator circuit can be used as the clock source for Timer1 and Timer3, simultaneously. Any of the SOSCEN bits will enable the secondary oscillator circuit and select it as the clock source for that particular timer. Table 13-2 displays the clock source selections.
13.2.1 INTERNAL CLOCK SOURCE
When the internal clock source is selected the TMRxH:TMRxL register pair will increment on multiples of FOSC as determined by the Timer1/3 prescaler.
When the FOSC internal clock source is selected, the Timer1/3 register value will increment by four counts every instruction clock cycle. Due to this condition, a 2 LSB error in resolution will occur when reading the Timer1/3 value. To utilize the full resolution of Timer1/3, an asynchronous input signal must be used to gate the Timer1/3 clock input.
The following asynchronous sources may be used:
• Asynchronous event on the TxG pin to Timer1/3 gate
• C1 or C2 comparator input to Timer1/3 gate 13.2.2 EXTERNAL CLOCK SOURCE When the external clock source is selected, the Timer1/3 module may work as a timer or a counter.
When enabled to count, Timer1/3 is incremented on the rising edge of the external clock input of the TxCKI pin.
This external clock source can be synchronized to the microcontroller system clock or it can run asynchronously.
When used as a timer with a clock oscillator, an external 32.768 kHz crystal can be used in conjunction with the dedicated secondary internal oscillator circuit.
TABLE 13-1: TIMER1/3 ENABLE SELECTIONS
TMRxON TMRxGE Timer1/3
Operation
0 0 Off
0 1 Off
1 0 Always On
1 1 Count Enabled
Note: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions:
• Timer1/3 enabled after POR
• Write to TMRxH or TMRxL
• Timer1/3 is disabled
• Timer1/3 is disabled (TMRxON = 0) when TxCKI is high then Timer1/3 is enabled (TMRxON=1) when TxCKI is low.
TABLE 13-2: CLOCK SOURCE SELECTIONS
TMRxCS1 TMRxCS0 SOSCEN Clock Source
0 1 x System Clock (FOSC)
0 0 x Instruction Clock (FOSC/4)
1 0 0 External Clocking on TxCKI Pin
1 0 1 Oscillator Circuit on SOSCI/SOSCO Pins
PIC18(L)F2X/45K50
13.3 Timer1/3 Prescaler
Timer1/3 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The TxCKPS bits of the TxCON register control the prescale counter. The prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write to TMRxH or TMRxL.
13.4 Secondary Oscillator
A dedicated secondary low-power 32.768 kHz oscillator circuit is built-in between pins SOSCI (input) and SOSCO (amplifier output). This internal circuit is to be used in conjunction with an external 32.768 kHz crystal.
The oscillator circuit is enabled by setting the SOSCEN bit of the TxCON register, the SOSCGO bit of the OSCCON2 register or by selecting the secondary oscillator as the system clock by setting SCS<1:0> = 01 in the OSCCON register. The oscillator will continue to run during Sleep.