1-3. コイン 1 枚を 2 回投げ，表が出る回数を n ˆ 。ただし，表が出る確率を p ，裏が出る確率を q とする。
1-4. コイン 1 枚を 3 回投げ，表が出る回数を n ˆ 。ただし，表が出る確率を p ，裏が出る確率を q とする。
問題 1. 確率 p で表，確率 1 − p で裏が出るコイン N 枚を一斉に投げる。それぞれのコインの振る舞いは独立 とする。コインに i = 1, . . . , N と名前をつけ， i 番目のコインが表なら 1 ，裏なら 0 という値をとる物理量 χ ˆ i を定義する。以下では，全系の確率分布を p と書く。
5-2. この系の状態数 Ω(E) を求めよ。系のマクロ性に対する近似 (E ≫ E 0 ) を用いてよい。
例題 2. 3 次元空間中の一辺 L ，体積 V = L 3 の立方体中の領域 (0 ≤ x, y, z ≤ L) だけを運動する N 個の自
由粒子からなる系について，系のエネルギー固有状態とエネルギー固有値，状態数 Ω(E) を求めよ。
自習 2. 2 次元空間中の一辺 L の箱 (0 ≤ x, y ≤ L) の中だけを自由に運動する質量 m の自由粒子に対して，
いた。鎖の両端をそれぞれ A と B ，また A から x 離れた点を P とする。 B を力 F で水平に引っ張ると全体が加速度 a で動いた。
19-1. 運動の様子を図示せよ。点 P における鎖の張力を S とする。 【解答】右図の通り。図の S は， A ∼ P 部分を右に引く張力である。もちろ ん実際には P で鎖はくっついているが， S が A ∼ P 部分に働くことを明らか にするため少し離して書いた。図の左向きの力は， S の反作用であり， P ∼ B 部分を左に引いている。
Received: 14 November 2011 / Accepted: 26 June 2012 / Published online: 13 July 2012 # Springer Science+Business Media, LLC 2012
Abstract The paper proposes a hierarchical untestable stuck-at fault identification method for non-scan synchro- nous sequential circuits. The method is based on deriving, minimizing and solving test path constraints for modules embedded into Register-Transfer Level (RTL) designs. First, an RTL test pattern generator is applied in order to extract the set of all possible test path constraints for a module under test. Then, the constraints are minimized using an SMT solver Z3 and a logic minimization tool ESPRESSO. Finally, a constraint-driven deterministic test pattern gener- ator is run providing hierarchical test generation and untest- ability proof in sequential circuits. We show by experiments that the method is capable of quickly proving a large num- ber of untestable faults obtaining higher fault efficiency than achievable by a state-of-the-art commercial ATPG. As a side effect, our study shows that traditional bottom-up test
Keywords: consecutive testability, consecutive transparency, test access mechanism, system-on-a-chip, design for testability, built-in self test
A fundamental change has taken place in the way digital systems are designed. It has become possible to design an entire system, containing millions of transis- tors, on a single chip. In order to cope with the growing complexity of such modern systems, designers often use pre-designed, reusable megacells knows as cores. Core-based systems-on-a-chip (SoC) design strategies help companies significantly reduce the time-to-market and design cost for their new products.
Although the security level of SR-quasi-equivalents is almost the same as that of SR-equivalents, there are several merits when
Fig. 10 Covering relation among classes.
applying SR-quasi-equivalents to the scan chain. One merit is as follows. From Fig. 10, we can see all the circuits in I 2 SR, LF 2 SR, and I 2 LF 2 SR are SR-quasi-equivalent, and hence we can use any of them to organize the secure and testable scan chains which means it is very easy to design an SR-quasi-equivalent circuit. Another merit is as follows. As for the influence on test power due to shift register modification, the insertion of inverters and/or XOR gates can reduce test power even more than standard scan design if they are inserted appropriately. However, such modi- fied shift registers are not always SR-equivalent but mostly SR- quasi-equivalent. Hence, SR-quasi-equivalent circuits are useful to easily organize modified scan chains that satisfy low-power testing as well as security and testability similar to SR-equivalent circuits.
Although the structure of a GSR is hard to be identi- fied, it may not be secure if part of the contents of the GSR leak out. To avoid such leakage, we consider more secure scan registers whose contents never leak out. First, we de- fine several concepts in the following. Consider a circuit C with a single input, a single output, and k flip-flops. C is called to be scan-in secure if for any internal state of C a transfer sequence (of length k) to the state (final state) can be generated only from the connection information of C, inde- pendently of the initial state, such that the transfer sequence is always different from that of a k-stage shift register. C is called to be scan-out secure if any present state (initial state) of C can be identified only from the input-output sequence (of length k) and the connection information of C, such that the output sequence is always different from that of a k-stage shift register. C is called to be strongly secure if C is scan-in secure and scan-out secure.
The previous works show that DFT methods treat data path and controller separately. In fact, they need the insertion of additional hardware, like a test controller to control the data transfer from the primary input to the targeted fault and from the targeted fault to the primary output. In this paper, we introduce a new DFT method using a high level modeling known as Assignment Decision Diagram (ADD)  extended from the previous work that has been done in . Different from , we abstract the DFT from the gate level and extend it to RTL. Additionally, our DFT method treats data path and controller unanimously. The DFT method augments a given RTL circuit based on the testability properties called thru function. We extract the thru function from the high level description of a given RTL circuit. Our method will improve test generation time and test application time as well as fault efficiency.