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[PDF] Top 20 C215 2010 4 DDECS 最近の更新履歴 Hideo Fujiwara

Has 10000 "C215 2010 4 DDECS 最近の更新履歴 Hideo Fujiwara" found on our website. Below are the top 20 most common "C215 2010 4 DDECS 最近の更新履歴 Hideo Fujiwara".

C215 2010 4 DDECS 最近の更新履歴  Hideo Fujiwara

C215 2010 4 DDECS 最近の更新履歴 Hideo Fujiwara

... Keywords - scan design; shift register equivalents; security; testability; cardinality; enumeration. I. I NTRODUCTION Both testability and security of a chip have become primordial to ensure its reliability and ... 完全なドキュメントを参照

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J154 e MJCS 2010 1 最近の更新履歴  Hideo Fujiwara J154 e MJCS 2010 1

J154 e MJCS 2010 1 最近の更新履歴 Hideo Fujiwara J154 e MJCS 2010 1

... Science City, 630-0192 Japan. *{norlina,ooichiayee,zuri}@fke.utm.my, +fujiwara@is.naist.jp ABSTRACT This paper introduces a new class of assignment decision diagrams (ADD) called thru-testable ADDs based on a ... 完全なドキュメントを参照

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C224 2010 11 ITC 最近の更新履歴  Hideo Fujiwara

C224 2010 11 ITC 最近の更新履歴 Hideo Fujiwara

... modes applied (TM) by the proposed method in Columns 2, 3, and 4, respectively. The column heading Original indicates the case when the original functional test sequence is applied on a given design, whereas the ... 完全なドキュメントを参照

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C214 2010 3 DTIS 最近の更新履歴  Hideo Fujiwara

C214 2010 3 DTIS 最近の更新履歴 Hideo Fujiwara

... MU X 1 in Figure 4. E. Algorithm for identification For an RTL circuit, the proposed method traverses RTL paths from each primary input or register until reaching a primary output or a register with depth-first ... 完全なドキュメントを参照

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J151 e JETTA 2010 4 最近の更新履歴  Hideo Fujiwara J151 e JETTA 2010 4

J151 e JETTA 2010 4 最近の更新履歴 Hideo Fujiwara J151 e JETTA 2010 4

... To increase the testability of the complete design and to ease RT-level test generation, various DFT methods at RT-level have also been proposed. The most com- mon methods are based on full-scan or partial scan. However, ... 完全なドキュメントを参照

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C216 2010 4 DDECS 最近の更新履歴  Hideo Fujiwara

C216 2010 4 DDECS 最近の更新履歴 Hideo Fujiwara

... E-mail: {ohtake, hiroshi-i, fujiwara}@is.naist.jp Abstract—This paper proposes a new synthesis method for propagating information of paths from register transfer level (RTL) to gate level. The method enables false ... 完全なドキュメントを参照

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J153 e IEICE 2010 7 最近の更新履歴  Hideo Fujiwara J153 e IEICE 2010 7

J153 e IEICE 2010 7 最近の更新履歴 Hideo Fujiwara J153 e IEICE 2010 7

... of equivalence checking (steps 4 and 5) is reduced if the number of candidates is efficiently decreased by the fault di- agnosis method (steps 2 and 3). Here, we assume that the fault diagnosis technique used in ... 完全なドキュメントを参照

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C222 2010 10 ISCIT 最近の更新履歴  Hideo Fujiwara

C222 2010 10 ISCIT 最近の更新履歴 Hideo Fujiwara

... IV. E XPERIMENTAL R ESULTS In our experiments, we applied both F-scan and gate- level full scan to ITC’99 Benchmark Circuits. F-scan is applied based on the heuristic algorithm described in our previous work [3], ... 完全なドキュメントを参照

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C213 2010 1 DELTA 最近の更新履歴  Hideo Fujiwara

C213 2010 1 DELTA 最近の更新履歴 Hideo Fujiwara

... Several false path identification methods at gate level for combinational circuits[1], [2], [3] and for sequential circuits[4], [5] have been proposed. However, since it is dif- ficult to apply false path ... 完全なドキュメントを参照

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C223 2010 11 ITC 最近の更新履歴  Hideo Fujiwara

C223 2010 11 ITC 最近の更新履歴 Hideo Fujiwara

... 2.1 Related Works Several DFT techniques at RTL have been proposed, most are scan-based. Gupta et al. [3] introduced a structured partial scan design that converts only the selected flip-flops into scan flip-flops. ... 完全なドキュメントを参照

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J152 e IEICE 2010 6 最近の更新履歴  Hideo Fujiwara J152 e IEICE 2010 6

J152 e IEICE 2010 6 最近の更新履歴 Hideo Fujiwara J152 e IEICE 2010 6

... In Table 5, Columns 3 and 4 denote the system-level cost and the corresponding test time of [3] for each TAM width in the above two scenarios. Columns 5 and 6 denote the system-level cost and the corresponding ... 完全なドキュメントを参照

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J150 e IEICE 2010 1 最近の更新履歴  Hideo Fujiwara J150 e IEICE 2010 1

J150 e IEICE 2010 1 最近の更新履歴 Hideo Fujiwara J150 e IEICE 2010 1

... 1. Introduction In recent years, very large scale integrated circuit (VLSI) testing has become increasingly important because of the rapidly increasing number of gates on VLSIs and the grow- ing complexity of VLSIs due ... 完全なドキュメントを参照

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C228 2010 12 WRTLT 最近の更新履歴  Hideo Fujiwara

C228 2010 12 WRTLT 最近の更新履歴 Hideo Fujiwara

... Keywords—design-for-testability; scan design; shift register equivalents; security; scan-based side-channel attack. I. I NTRODUCTION The design of secure chips demands protection of secret information, which may cause ... 完全なドキュメントを参照

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C227 2010 12 ATS 最近の更新履歴  Hideo Fujiwara

C227 2010 12 ATS 最近の更新履歴 Hideo Fujiwara

... Table 1 describes the test application time and test power reductions for the test set using MT-filling. Since TetraMAX cannot realize MT-filling to the test vectors for PIs, we apply MT-filling after test generation. ... 完全なドキュメントを参照

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C225 2010 12 ATS 最近の更新履歴  Hideo Fujiwara

C225 2010 12 ATS 最近の更新履歴 Hideo Fujiwara

... number of LSSD scan elements, it involves high area and performance overhead. To resolve these problems, several scan-based approaches have been proposed. These can be classified into two categories: partial scan and full ... 完全なドキュメントを参照

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C231 2010 12 APCCAS 最近の更新履歴  Hideo Fujiwara

C231 2010 12 APCCAS 最近の更新履歴 Hideo Fujiwara

... • More test resources are given to the upper layer (i.e. layer 2) in order to increase the scheduling flexibility, which would result in a more thermal-efficient test schedule. This is based on our earlier observation on ... 完全なドキュメントを参照

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C212 2010 1 ASPDAC 最近の更新履歴  Hideo Fujiwara

C212 2010 1 ASPDAC 最近の更新履歴 Hideo Fujiwara

... Several works have been proposed to solve this challenging problem. A scan-chain design based on scrambling was proposed in [4], [5]. In this method, flip-flops are dynamically reordered in a scan chain. An ... 完全なドキュメントを参照

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C221 2010 7 IOLTS 最近の更新履歴  Hideo Fujiwara

C221 2010 7 IOLTS 最近の更新履歴 Hideo Fujiwara

... Some examples of the TPS movements are also shown in Fig. 7. According to the result of an aging analysis, a TPS can move from the scheduling table to the first level danger table like the TPS 9, but can jump to a two or ... 完全なドキュメントを参照

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C220 2010 5 GLSVLSI 最近の更新履歴  Hideo Fujiwara

C220 2010 5 GLSVLSI 最近の更新履歴 Hideo Fujiwara

... As discussed in the previous section, peak power reduction is becoming increasingly important. A few works have been proposed in peak power reduction [10, 7, 6, 8, 2]. Sankar- alingam et al. [10] first identify the peak ... 完全なドキュメントを参照

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C230 2010 12 WRTLT 最近の更新履歴  Hideo Fujiwara

C230 2010 12 WRTLT 最近の更新履歴 Hideo Fujiwara

... In this paper we propose to have a broader look at the discussed above problem of TPG for manufacturing test. The preceding phases of an ASIC development flow (Figure 1) normally include the design phase which is tightly ... 完全なドキュメントを参照

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