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[PDF] Top 20 C100 2003 11 ATS 最近の更新履歴 Hideo Fujiwara

Has 10000 "C100 2003 11 ATS 最近の更新履歴 Hideo Fujiwara" found on our website. Below are the top 20 most common "C100 2003 11 ATS 最近の更新履歴 Hideo Fujiwara".

C100 2003 11 ATS 最近の更新履歴  Hideo Fujiwara

C100 2003 11 ATS 最近の更新履歴 Hideo Fujiwara

... A software based self-test approach targeting delay faults was proposed by Lai et. al [10,11,12]. This approach, first classifies a path to be functionally testable or untestable. The authors argue that delay ... 完全なドキュメントを参照

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C102 2003 11 ATS 最近の更新履歴  Hideo Fujiwara

C102 2003 11 ATS 最近の更新履歴 Hideo Fujiwara

... using the sequence transformation. (c) Transform T into a test sequence T for f in S. As mentioned previously, a TEG of a acyclic sequential circuit is unique if the circuit is a single-output one. There- fore, in ... 完全なドキュメントを参照

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C98 2003 11 ATS 最近の更新履歴  Hideo Fujiwara

C98 2003 11 ATS 最近の更新履歴 Hideo Fujiwara

... Ccurrent (line7). The following process are performed on all DFTs of each core (line8-line20). C is updated by the test cost information C’ that DFT was changed about one core (line10 - 11). Test scheduling is ... 完全なドキュメントを参照

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C99 2003 11 ATS 最近の更新履歴  Hideo Fujiwara

C99 2003 11 ATS 最近の更新履歴 Hideo Fujiwara

... Email:fujiwara@is.aist-nara.ac.jp Abstract This paper proposes a test generation method using several partly compacted test plan tables for RTL data paths. Combinational modules in data paths are tested using ... 完全なドキュメントを参照

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C101 2003 11 ATS 最近の更新履歴  Hideo Fujiwara

C101 2003 11 ATS 最近の更新履歴 Hideo Fujiwara

... Our group proposed another test synthesis methods based on strong testability [7, 8, 9, 10, 11]. This testability guarantees all the modules including multiplexors(MUXs) in a datapath to be tested hierarchically. ... 完全なドキュメントを参照

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C95 2003 11 ATS 最近の更新履歴  Hideo Fujiwara

C95 2003 11 ATS 最近の更新履歴 Hideo Fujiwara

... In our approach, the maximal number of partitions per test is three. In the example (Figure 4), no test is partitioned into more than two partitions. However, if the test at c 2 would terminate after time 1 but ... 完全なドキュメントを参照

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C104 2003 11 WRTLT 最近の更新履歴  Hideo Fujiwara

C104 2003 11 WRTLT 最近の更新履歴 Hideo Fujiwara

... Let PCGT=(T, E c) be a sub-graph of PCG, which only contains all nodes corresponding to the test vectors set T. If the sub-graph PCG T is unconnected, we cannot obtain a test sequence which traverses all the nodes ... 完全なドキュメントを参照

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C105 2003 11 WRTLT 最近の更新履歴  Hideo Fujiwara

C105 2003 11 WRTLT 最近の更新履歴 Hideo Fujiwara

... This paper also presents a power constrained test synthesis and scheduling algorithm for adjacent non-scan BIST scheme intended for short test application time.. Int[r] ... 完全なドキュメントを参照

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C89 2003 3 DATE 最近の更新履歴  Hideo Fujiwara

C89 2003 3 DATE 最近の更新履歴 Hideo Fujiwara

... pseudo-transformation techniques[1, 8, 9, 10, 11]. In this paper, we target to ease test generation. The SFT and DFT techniques can make a given combinational cir- cuit easily testable at the cost of additional ... 完全なドキュメントを参照

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C92 2003 5 ETW 最近の更新履歴  Hideo Fujiwara

C92 2003 5 ETW 最近の更新履歴 Hideo Fujiwara

... With the increasing speed and complexity of VLSI cir- cuits, tests targeted only for stuck-at faults are insufficient to guarantee the proper circuit operation. Delay testing is necessary to reach the acceptable quality ... 完全なドキュメントを参照

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C93 2003 5 ETW 最近の更新履歴  Hideo Fujiwara

C93 2003 5 ETW 最近の更新履歴 Hideo Fujiwara

... [6] S. Ravi, G. Lakshminarayana, and N. K. Jha. TAO: Regular expres- sion based register-transfer level testability analysis and optimization. IEEE Trans. on VLSI Systems , 9(11):357–370, Dec. 2001. [7] H. Wada, ... 完全なドキュメントを参照

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C91 2003 5 VTS 最近の更新履歴  Hideo Fujiwara

C91 2003 5 VTS 最近の更新履歴 Hideo Fujiwara

... However, it is difficult to test SoCs after fabrication[1]. A major problem to make an SoC testable concerns acces- sibility of embedded cores. Several design-for-testability (DFT) techniques have been proposed. There are ... 完全なドキュメントを参照

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11 IEICE 最近の更新履歴  Hideo Fujiwara

11 IEICE 最近の更新履歴 Hideo Fujiwara

... セキュアスキャン設計ためシフトレジスタ等価回路列挙と合成 藤原 克哉 † a) 藤原 秀雄 †† オビエン マリー エンジェリン †† 玉本 英夫 † Enumeration and Synthesis of Shift Register Equivalents for Secure Scan Design Katsuya FUJIWARA †a) , Hideo FUJIWARA †† ... 完全なドキュメントを参照

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J106 j IEICE 2003 9 最近の更新履歴  Hideo Fujiwara J106 j IEICE 2003 9

J106 j IEICE 2003 9 最近の更新履歴 Hideo Fujiwara J106 j IEICE 2003 9

... 諸氏に 感謝し ます.本研究は 一部,奈良先端科学技 術大学院大学支援財団教育研究活動支援による. 文 献 [1] A. Balakrishman and S.T. Chakradhar, “Sequential circuits with combinational test generation complex- ity,” IEEE International Conference on VLSI Design, ... 完全なドキュメントを参照

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J104 j IEICE 2003 7 最近の更新履歴  Hideo Fujiwara J104 j IEICE 2003 7

J104 j IEICE 2003 7 最近の更新履歴 Hideo Fujiwara J104 j IEICE 2003 7

... など 既存手法を用いて ,組合せ回路要素単 体に対し ては十分な故障検出率が 得られ るものとする. これら手法では ,デ ータパスに対し てはテ ストプ ラ ンを生成する.テ ストプ ラン とは ,ゲートレ ベル故 障シミュレ ーシ ョンで与えたパターンと同じ パターン を与え るために ,デ ータパス中各組合せ回路要素に 対し て , TPG ... 完全なドキュメントを参照

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J103 e IEICE 2003 6 最近の更新履歴  Hideo Fujiwara J103 e IEICE 2003 6

J103 e IEICE 2003 6 最近の更新履歴 Hideo Fujiwara J103 e IEICE 2003 6

... However, to make the delay testing consistent with the overall operation of a controller- data path circuit, we resort to segment delay fault model for MUX select lines and register load[r] ... 完全なドキュメントを参照

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J102 e IPSJ 2003 5 最近の更新履歴  Hideo Fujiwara J102 e IPSJ 2003 5

J102 e IPSJ 2003 5 最近の更新履歴 Hideo Fujiwara J102 e IPSJ 2003 5

... MPEG N/A 224.47 17.64 N/A 423573 150019 N/A 100.00 100.00 path” columns list the characteristics of the controller parts and data path parts, respec- tively; the “#PI”, “#PO”, and “Area” columns list the ... 完全なドキュメントを参照

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11 WRTLT 最近の更新履歴  Hideo Fujiwara

11 WRTLT 最近の更新履歴 Hideo Fujiwara

... fujiwara@ogu.ac.jp Abstract—Scan design makes digital circuits easily testable, however, it can also be exploited to be used for hacking the chip. We have reported a secure and testable scan design approach by ... 完全なドキュメントを参照

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C94 2003 9 ITC 最近の更新履歴  Hideo Fujiwara

C94 2003 9 ITC 最近の更新履歴 Hideo Fujiwara

... 3 Area and Time Co-Optimization In this section, we present an area overhead and test time co-optimization method based on consecutive testabil- ity. The method creates TAM and a test schedule, and aug- ments a given SoC ... 完全なドキュメントを参照

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C90 2003 5 VTS 最近の更新履歴  Hideo Fujiwara

C90 2003 5 VTS 最近の更新履歴 Hideo Fujiwara

... SE-582 83 Linkoping, Sweden 8916-5 Takayama, Ikoma, Nara 630-0101, Japan erila@ida.liu.se fujiwara@is.aist-nara.ac.jp Abstract 1 We propose a test resource partitioning and optimization technique for core-based ... 完全なドキュメントを参照

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