トップPDF C100 2003 11 ATS 最近の更新履歴 Hideo Fujiwara

C100 2003 11 ATS 最近の更新履歴  Hideo Fujiwara

C100 2003 11 ATS 最近の更新履歴 Hideo Fujiwara

A software based self-test approach targeting delay faults was proposed by Lai et. al [10,11,12]. This approach, first classifies a path to be functionally testable or untestable. The authors argue that delay defects on the functionally untestable paths will not cause any chip failure. They also suggest that gross delay defects should be tested by transition fault testing. In their method datapath and controller are considered separately. Path classification is performed by extracting a set of constraints for the datapath logic and the controller. In constraint extraction procedure for datapath, all instruction pairs are enumerated and for each instruction pair all possible vector pairs that can be applied to the datapath are derived symbolically. These symbolic vector pairs represent the constraints for datapath testing. This requires a substantial effort to analyze all the instructions and all possible pairs of instructions even though it is not necessary to analyze all the pairs as shown in this paper. For controller, constraints in terms of legitimate bit patterns in registers and correlation between control signals and transition in registers are extracted. A procedure given in [15] is used to classify paths in controller which uses multiple time frames. This procedure uses sequential path classification methodology i.e., in order to classify a path it propagate the transition forward till PO and backward till PI in multiple time frames under the constraints. This is needed because it is not extracting the constraints provided by the state transitions. After classification of paths, constrained ATPG is used to generate the test patterns for testable paths. Lai and Cheng [13] proposed an approach for delay fault testing of a System-on-a-Chip using its own embedded processor instructions, and also proposed a methodology to include new test instructions for testability enhancement and test program size reduction.
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C102 2003 11 ATS 最近の更新履歴  Hideo Fujiwara

C102 2003 11 ATS 最近の更新履歴 Hideo Fujiwara

using the sequence transformation. (c) Transform T into a test sequence T for f in S. As mentioned previously, a TEG of a acyclic sequential circuit is unique if the circuit is a single-output one. There- fore, in Step 3, E is also unique. In this paper, since we use a slow-fast-slow testing strategy in test application, a sequential circuit can be considered delay fault-free except in applying a fast clock. This implies that it is sufficient to generate a two-pattern test for at least one SDF in Step 4(a). In Step 4(c), T is always transformed into T by applying T to the primary inputs of S corresponding to the primary inputs of S c . Note that, for the other primary inputs of S,
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C98 2003 11 ATS 最近の更新履歴  Hideo Fujiwara

C98 2003 11 ATS 最近の更新履歴 Hideo Fujiwara

Ccurrent (line7). The following process are performed on all DFTs of each core (line8-line20). C is updated by the test cost information C’ that DFT was changed about one core (line10 - 11). Test scheduling is performed (line12). Consequently, if the obtained test application time is shorter than best_tat (line13), best_tat w ill be updated (line14) and test cost information C will be stored as Cbest (line15). After all DFTs of the concerned core are tried, C is written back to Ccurrent (line18). Then, after all

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C99 2003 11 ATS 最近の更新履歴  Hideo Fujiwara

C99 2003 11 ATS 最近の更新履歴 Hideo Fujiwara

Email:fujiwara@is.aist-nara.ac.jp Abstract This paper proposes a test generation method using several partly compacted test plan tables for RTL data paths. Combinational modules in data paths are tested using several partly compacted test plan tables. Each partly compacted test plan table is generated from each grouped test plan set and is used to test combinational modules corresponding to the grouped test plans. The values of control signals in a partly compacted test plan table are supplied from a test controller. This paper also proposes the architecture of a test controller which can be synthesized in a reasonable amount of time, and proposes a test plan grouping method to shorten test length for data paths under a test controller area constraint. Experimental results for benchmarks show that the test lengths are shortened by 4 to 36 % with -9 to 8 % additional test controller area compared with the test generation method using test plans.
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C101 2003 11 ATS 最近の更新履歴  Hideo Fujiwara

C101 2003 11 ATS 最近の更新履歴 Hideo Fujiwara

Our group proposed another test synthesis methods based on strong testability [7, 8, 9, 10, 11]. This testability guarantees all the modules including multiplexors(MUXs) in a datapath to be tested hierarchically. This robust prop- erty is necessary to become an alternative to the scan de- sign. We derived test plans, which are sequences of control signals that form control and observation paths for modules under test. We have an isolation approach and an integra- tion approach. In the isolation approach, a datapath and a controller are considered independently, and test plans are provided from a test plan generator embedded for at-
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C95 2003 11 ATS 最近の更新履歴  Hideo Fujiwara

C95 2003 11 ATS 最近の更新履歴 Hideo Fujiwara

In our approach, the maximal number of partitions per test is three. In the example (Figure 4), no test is partitioned into more than two partitions. However, if the test at c 2 would terminate after time 1 but before 3 (LB) another partition would be created. In Figure 7 we show the general TAM bandwidth requirement for a test. The TAM bandwidth is equal for two of the sessions since n 1 =n 3 (Figure 7). It means that only two configurations are needed at each core and a multiplexer for selection between w 1 and

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C104 2003 11 WRTLT 最近の更新履歴  Hideo Fujiwara

C104 2003 11 WRTLT 最近の更新履歴 Hideo Fujiwara

Let PCGT=(T, E c) be a sub-graph of PCG, which only contains all nodes corresponding to the test vectors set T. If the sub-graph PCG T is unconnected, we cannot obtain a test sequence which traverses all the nodes of T. In this case, we need to add some new test vectors from outside of T. Furthermore, even if PCGT is connected, adding some new test vectors may decrease the test sequence length. Therefore, we augment the sub-graph PCG T by adding some nodes (for new test vectors) and corresponding edges from PCG so that augmented sub-graph contains a shortest test sequence.
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C105 2003 11 WRTLT 最近の更新履歴  Hideo Fujiwara

C105 2003 11 WRTLT 最近の更新履歴 Hideo Fujiwara

This paper also presents a power constrained test synthesis and scheduling algorithm for adjacent non-scan BIST scheme intended for short test application time.. Int[r]

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C89 2003 3 DATE 最近の更新履歴  Hideo Fujiwara

C89 2003 3 DATE 最近の更新履歴 Hideo Fujiwara

pseudo-transformation techniques[1, 8, 9, 10, 11]. In this paper, we target to ease test generation. The SFT and DFT techniques can make a given combinational cir- cuit easily testable at the cost of additional hardware and in- creased delay. Therefore we aim to make a new test genera- tion methodology for PDFs in combinational circuits within

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C92 2003 5 ETW 最近の更新履歴  Hideo Fujiwara

C92 2003 5 ETW 最近の更新履歴 Hideo Fujiwara

With the increasing speed and complexity of VLSI cir- cuits, tests targeted only for stuck-at faults are insufficient to guarantee the proper circuit operation. Delay testing is necessary to reach the acceptable quality level. Until now, several delay fault models have been investigated [9]. The path delay fault model [11] is one of the most general mod- els among them because distributed faults along paths can be tested and the delay size of detectable faults is scalable.

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C93 2003 5 ETW 最近の更新履歴  Hideo Fujiwara

C93 2003 5 ETW 最近の更新履歴 Hideo Fujiwara

[6] S. Ravi, G. Lakshminarayana, and N. K. Jha. TAO: Regular expres- sion based register-transfer level testability analysis and optimization. IEEE Trans. on VLSI Systems , 9(11):357–370, Dec. 2001. [7] H. Wada, T. Masuzawa, K. K. Saluja, and H. Fujiwara. Design for strong testability of RTL data paths to provide complete fault effi- ciency. In 13th International Conference on VLSI Design, pages 300– 305, Jan. 2000.

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C91 2003 5 VTS 最近の更新履歴  Hideo Fujiwara

C91 2003 5 VTS 最近の更新履歴 Hideo Fujiwara

However, it is difficult to test SoCs after fabrication[1]. A major problem to make an SoC testable concerns acces- sibility of embedded cores. Several design-for-testability (DFT) techniques have been proposed. There are three main approaches to achieve accessibility of embedded cores. The first approach is based on test bus architectures by which the cores are isolated from each other in test mode using a dedicated bus [4, 5, 6, 7, 8] or flexible TESTRAIL [9] around the cores to propagate test data. The second approach uses boundary scan architectures [2, 3] to isolate the core during test. The third approach uses transparency [11, 12, 13, 10] for embedded cores to reduce the problem to one of finding paths from PIs to core inputs and from core outputs to POs. Under the design environment for SoCs, pre-computed test sets are provided for each core. These test sets may
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11 IEICE 最近の更新履歴  Hideo Fujiwara

11 IEICE 最近の更新履歴 Hideo Fujiwara

セキュアスキャン設計ためシフトレジスタ等価回路列挙と合成 藤原 克哉 † a) 藤原 秀雄 †† オビエン マリー エンジェリン †† 玉本 英夫 † Enumeration and Synthesis of Shift Register Equivalents for Secure Scan Design Katsuya FUJIWARA †a) , Hideo FUJIWARA †† , Marie E. J. OBIEN †† ,

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J106 j IEICE 2003 9 最近の更新履歴  Hideo Fujiwara J106 j IEICE 2003 9

J106 j IEICE 2003 9 最近の更新履歴 Hideo Fujiwara J106 j IEICE 2003 9

諸氏に 感謝し ます.本研究は 一部,奈良先端科学技 術大学院大学支援財団教育研究活動支援による. 文 献 [1] A. Balakrishman and S.T. Chakradhar, “Sequential circuits with combinational test generation complex- ity,” IEEE International Conference on VLSI Design, pp.111–117, Jan. 1996.

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J104 j IEICE 2003 7 最近の更新履歴  Hideo Fujiwara J104 j IEICE 2003 7

J104 j IEICE 2003 7 最近の更新履歴 Hideo Fujiwara J104 j IEICE 2003 7

本論文では, RTL におけるテスト 容易化設計法を提 案する.ゲ ートレ ベルに 対し ては ,テストポ イント 挿 入 [10] など 既存手法を用いて ,組合せ回路要素単 体に対し ては十分な故障検出率が 得られ るものとする. これら手法では ,デ ータパスに対し てはテ ストプ ラ ンを生成する.テ ストプ ラン とは ,ゲートレ ベル故 障シミュレ ーシ ョンで与えたパターンと同じ パターン を与え るために ,デ ータパス中各組合せ回路要素に 対し て , TPG からテスト パターン 伝搬と RA で 応答観測ために与え る制御信号線上信号時 系列である.また ,コント ローラに 対し ては ,本論文 では 状態レジ スタを CBILBO に 置き換え ることに よ り階層 BIST を実現する.
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J103 e IEICE 2003 6 最近の更新履歴  Hideo Fujiwara J103 e IEICE 2003 6

J103 e IEICE 2003 6 最近の更新履歴 Hideo Fujiwara J103 e IEICE 2003 6

However, to make the delay testing consistent with the overall operation of a controller- data path circuit, we resort to segment delay fault model for MUX select lines and register load[r]

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J102 e IPSJ 2003 5 最近の更新履歴  Hideo Fujiwara J102 e IPSJ 2003 5

J102 e IPSJ 2003 5 最近の更新履歴 Hideo Fujiwara J102 e IPSJ 2003 5

MPEG N/A 224.47 17.64 N/A 423573 150019 N/A 100.00 100.00 path” columns list the characteristics of the controller parts and data path parts, respec- tively; the “#PI”, “#PO”, and “Area” columns list the numbers of primary inputs and pri- mary outputs and the circuit area of respective parts. The “#State”, “#Status”, and “#Con- trol” columns in the “Controller” part of Ta- ble 3 list the numbers of states, status inputs, and control outputs. The “|bit|”, “#Reg.”, and “#Mod”. columns in the “Data path” part of the table list the bit widths of data paths and the numbers of registers and operational mod- ules they contain. In the row labeled “RISC”, the number of status signals is larger than that of the primary inputs of the data path. In our DFT, twenty-two primary output pins are changed into primary input and output pins by appending tri-state buffers. However, the hard- ware overhead of this modification is negligible. The test generation results are shown in Table 4. The sequential and combinational ATPG tool TestGen (Synopsys) was used in this experiment on an Ultra60 model 2360 (Sun- Microsystems). The “Test generation time”, “Test application time”, and “Fault efficiency” columns list the test generation time in second, test application time in clock cycles, and the fault efficiency. In each of these columns, the subcolumns labeled “Original”, “Full-scan”, and “Our method” list the results for the orig- inal circuits (without DFT), for the circuits modified by full-scan design, and for the circuits modified by our method. The time required to make a data path strongly testable and gener- ate test plans for combinational hardware ele- ments is included in the test generation time of our method. For the original MPEG circuit, TestGen did not finish within a week. The test generation time of our method is shorter than that of full-scan design except in the case of LWF. In particular, for the RISC circuit, our method can reduce the time to 1/700 of that for full-scan design, and can achieve higher fault ef- ficiency. For this circuit, the fault efficiency is 99.99%, because the combinational ATPG tool
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11 WRTLT 最近の更新履歴  Hideo Fujiwara

11 WRTLT 最近の更新履歴 Hideo Fujiwara

fujiwara@ogu.ac.jp Abstract—Scan design makes digital circuits easily testable, however, it can also be exploited to be used for hacking the chip. We have reported a secure and testable scan design approach by using extended shift registers called “SR-equivalents” that are functionally equivalent but not structurally equivalent to shift registers [14-17]. In this paper, to further extend the class of SR- equivalents we introduce a wider class of circuits called “SR- quasi-equivalents” which still satisfy the testability and security similar to SR-equivalents. To estimate the security level, we clarify the cardinality of each equivalent class in SR-quasi- equivalents for several linear structural circuits, and also present the actual number of SR-quasi-equivalents obtained by the enhanced program SREEP.
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C94 2003 9 ITC 最近の更新履歴  Hideo Fujiwara

C94 2003 9 ITC 最近の更新履歴 Hideo Fujiwara

3 Area and Time Co-Optimization In this section, we present an area overhead and test time co-optimization method based on consecutive testabil- ity. The method creates TAM and a test schedule, and aug- ments a given SoC into consecutively testable one by adding extra circuits (design-for-testability (DFT) elements) where area overhead and test time are co-optimized. When we cre- ate consecutively test accessible TAM, we consider test bus (Figure 4(a)), consecutive transparency (Figure 4(b)), direct path from a PI to a core (from a core to a PO) with mul- tiplexer (Figure 4(c)) and existing interconnect as compo-
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C90 2003 5 VTS 最近の更新履歴  Hideo Fujiwara

C90 2003 5 VTS 最近の更新履歴 Hideo Fujiwara

SE-582 83 Linkoping, Sweden 8916-5 Takayama, Ikoma, Nara 630-0101, Japan erila@ida.liu.se fujiwara@is.aist-nara.ac.jp Abstract 1 We propose a test resource partitioning and optimization technique for core-based designs. Our technique includes test set selection and test resource floor-planning with the aim of minimizing the total test application time and the routing of the added TAM (test access mechanism) wires. A feature of our approach is that it pinpoints bottlenecks that are likely to limit the test solution, which is important in the iterative test solution development process. We demonstrate the usefulness of the technique through a comparison with a test scheduling and TAM design tool.
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