© Semiconductor Components Industries, LLC, 2006
April, 2006 − Rev. 1 1 Publication Order Number:
NID5004N/D
Self−Protected FET
with Temperature and Current Limit
40 V, 6.5 A, Single N−Channel, DPAK
Self–protected FETs are a series of power MOSFETs which utilize ON Semiconductor HDPlus t technology. The self–protected MOSFET incorporates protection features such as integrated thermal and current limits. The self−protected MOSFETs include an integrated Drain−to−Gate Clamp that provides overvoltage protection from transients and avalanche. The device is protected from Electrostatic Discharge (ESD) by utilizing an integrated Gate−to−Source Clamp.
Features
• Short Circuit Protection
• In Rush Current Limit
• Thermal Shutdown with Automatic Restart
• Avalanche Rated
• Overvoltage Protection
• ESD Protection (4 kV HBM)
• Controlled Slew Rate for Low Noise Switching
• AEC Q101 Qualified
• This is a Pb−Free Device
Applications• Solenoid Driver
• Relay Driver
• Small Motors
• Lighting
• Relay Replacement
• Load Switching
Device Package Shipping† ORDERING INFORMATION DPAK
CASE 369C STYLE 2
Drain
Source Temperature
Limit Gate
Input
MARKING DIAGRAM
D5004N = Device Code
Y = Year
WW = Work Week G = Pb−Free Device
Current
Limit Current Sense RG
Overvoltage Protection
ESD Protection
YYW D5 004NG
1 = Gate 2 = Drain 3 = Source 1
2 3 VDSS
(Clamped) RDS(on) Typ ID Typ (Limited) 40 V 110 mW @ 10 V 6.5 A
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
http://onsemi.com
NID5004NT4G DPAK
(Pb−Free) 2500/Tape & Reel
MOSFET MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating Symbol Value Unit
Drain−to−Source Voltage Internally Clamped VDSS 44 Vdc
Gate−to−Source Voltage VGS "14 Vdc
Drain Current Continuous ID Internally Limited
Total Power Dissipation
@ TA = 25°C (Note 1)
@ TA = 25°C (Note 2)
PD
1.32.5
W
Thermal Resistance Junction−to−Case
Junction−to−Ambient (Note 1) Junction−to−Ambient (Note 2)
RqJC RqJA RqJA
3.095 50
°C/W
Single Pulse Drain−to−Source Avalanche Energy (VDD = 30 Vdc, VGS = 5.0 Vdc,
IL = 1.8 Apk, L = 160 mH, RG = 25 W) (Note 3)
EAS 273 mJ
Operating and Storage Temperature Range (Note 4) TJ, Tstg −55 to 150 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
1. Surface mounted onto minimum pad size (100 sq/mm) FR4 PCB, 1 oz cu.
2. Mounted onto 1″ square pad size (700 sq/mm) FR4 PCB, 1 oz cu.
3. Not subject to Production Test
4. Normal pre−fault operating range. See thermal limit range conditions.
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MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Clamped Breakdown Voltage
(VGS = 0 V, ID = 2 mA) V(BR)DSS
36 40 44 V
Zero Gate Voltage Drain Current
(VDS = 32 V, VGS = 0 V) IDSS
− 27 100 mA
Gate Input Current
(VGS = 5.0 V, VDS = 0 V) IGSS
− 45 200 mA
ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = 150 mA) Threshold Temperature Coefficient
VGS(th)
1.0− 1.85
5.0 2.2
− V
−mV/°C Static Drain−to−Source On−Resistance (Note 5)
(VGS = 10 V, ID = 2.0 A, TJ @ 25°C) RDS(on)
− 110 130 mW
Static Drain−to−Source On−Resistance (Note 5) (VGS = 5.0 V, ID = 2.0 A, TJ @ 25°C)
(VGS = 5.0 V, ID = 2.0 A, TJ @ 150°C)
RDS(on)
−− 130
240 150
270
mW Source−Drain Forward On Voltage
(IS = 7.0 A, VGS = 0 V) VSD
− 0.9 1.1 V
SWITCHING CHARACTERISTICS (Note 6)
Turn−on Delay Time RL = 6.6 W, Vin = 0 to 10 V, VDD = 13.8 V, ID = 2.0 A, 10% Vin to 10% ID
td(on) − 97 115 ns
Turn−on Rise Time RL = 6.6 W, Vin = 0 to 10 V,
VDD = 13.8 V, ID = 2.0 A, 10% ID to 90% ID trise − 282 300 ns Turn−off Delay Time RL = 6.6 W, Vin = 0 to 10 V,
VDD = 13.8 V, ID = 2.0 A, 90% Vin to 90% ID
td(off) − 930 1020 ns
Turn−off Fall Time RL = 6.6 W, Vin = 0 to 10 V,
VDD = 13.8 V, ID = 2.0 A, 90% ID to 10% ID tfall − 690 750 ns Slew Rate ON RL = 6.6 W, Vin = 0 to 10 V,
VDD = 13.8 V, ID = 2.0 A, 70% to 50% VDD
dVDS/dTon − 64 − V/ms
Slew Rate OFF RL = 6.6 W, Vin = 0 to 10 V,
VDD = 13.8 V, ID = 2.0 A, 50% to 70% VDD dVDS/dToff − 28 − V/ms SELF PROTECTION CHARACTERISTICS(TJ = 25°C unless otherwise noted) (Note 7)
Current Limit VDS = 10 V, VGS = 5.0 V, TJ = 25°C (Note 8) VDS = 10 V, VGS = 5.0 V, TJ = 100°C (Note 6, 8)
VDS = 10 V, VGS = 10 V, TJ = 25°C (Note 6, 8)
ILIM 4.0
4.0− 6.55.5 7.9
1111
−
A
Temperature Limit (Turn−off) VGS = 5.0 V (Note 6) TLIM(off) 150 180 200 °C
Thermal Hysteresis VGS = 5.0 V DTLIM(on) − 10 − °C
Temperature Limit (Turn−off) VGS = 10 V (Note 6) TLIM(off) 150 180 200 °C
Thermal Hysteresis VGS = 10 V DTLIM(on) − 20 − °C
Input Current during
Thermal Fault VDS = 0 V, VGS = 5.0 V, TJ = TJ > T(fault) (Note 6)
VDS = 0 V, VGS = 10 V, TJ = TJ > T(fault) (Note 6) Ig(fault) 5.5
12 5.2
11 − mA
ESD ELECTRICAL CHARACTERISTICS(TJ = 25°C unless otherwise noted) Electrostatic Discharge Capability
Human Body Model (HBM) Machine Model (MM) (Note 6)
ESD 4000
400 −
− −
−
V
5. Pulse Test: Pulse Width ≤300 ms, Duty Cycle ≤ 2%.
6. Not subject to Production Test
7. Fault conditions are viewed as beyond the normal operating range of the part.
8. Current limit measured at 380 ms after gate pulse.
TYPICAL PERFORMANCE CURVES
TJ = 100°C
0 4
5.0
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) ID,DRAIN CURRENT (AMPS)
2 0
Figure 1. On−Region Characteristics
3 3
2
0
Figure 2. Transfer Characteristics VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 3. On−Resistance vs. Gate−to−Source Voltage
ID,DRAIN CURRENT (AMPS)
Figure 4. On−Resistance vs. Drain Current ID, DRAIN CURRENT (AMPS)
−55 −35 −15 5 1.4
1.6
1.0 0.8 0.6
25
Figure 5. On−Resistance Variation with Temperature
TJ, JUNCTION TEMPERATURE (°C)
TJ = 25°C TJ = −55°C
45
TJ = 25°C
ID = 3.75 A VGS = 10 V
RDS(on),DRAIN−TO−SOURCE RESISTANCE (W)
TJ = 25°C
RDS(on),DRAIN−TO−SOURCE RESISTANCE (W)
VGS = 10 V
0E+00
Figure 6. Drain−to−Source Leakage Current vs. Voltage
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
30 IDSS, LEAKAGE (A)
TJ = 100°C VGS = 5 V
10 40
4.0 V
1
4
45 6
10 V
4
85 65
5
0.13
0.10 0.14
0.11 0.12
4E−04
0 10
10 20
5
0 2
4.0
2.0 2.4 2.8
1.2
25 8
15
VGS = 3.0 V 3.5 V
3.2
12 6
1
0.15
8E−04
0.4
5.0 V
15 20
2E−04 6E−04 1E−03 VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
RDS(on),DRAIN−TO−SOURCE RESISTANCE (W) 0.10 0.12
0.11
10
3.0 5.0 7.0 9.0
0.15 ID = 2 A
TJ = 25°C
0.13 0.14
35 5.0
4.0 6.0 8.0 2.2 2.6 3.0 3.4 3.6 3.8
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TYPICAL PERFORMANCE CURVES
VDS = 0 V TA = 200°C
Figure 7. Diode Forward Voltage vs. Current Figure 8. Input Current vs. Gate Voltage 2000
0
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) IGSS (mA)
8 7
6 12000
8000 6000 4000
9
7E−3 2
0
TIME (seconds)
Figure 9. Short Circuit Response*
*(Actual thermal cycling response in short circuit dependent on device power level, thermal mounting, and ambient temperature conditions)
DRAIN CURRENT (AMPS)
4E−3 2E−3
0E+0 12
8
5E−3 3E−3
1E−3 6
4
6E−3 0.2
1 0
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) IS, SOURCE CURRENT (AMPS)
VGS = 0 V TJ = 25°C
5
0.8 0.6
4 3 2 6 7
0.4 8
1.0 0
10000
10
10 VGS = 10 V
VGS = 5 V
Current Limit
Temperature Limit
0.1 0.3 0.5 0.7 0.9
HDPlus is a trademark of Semiconductor Components Industries, LLC (SCILLC)
DPAK (SINGLE GAUGE) CASE 369C
ISSUE F
DATE 21 JUL 2015 SCALE 1:1
STYLE 1:
PIN 1. BASE 2. COLLECTOR 3. EMITTER 4. COLLECTOR
STYLE 2:
PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN
STYLE 3:
PIN 1. ANODE 2. CATHODE 3. ANODE 4. CATHODE
STYLE 4:
PIN 1. CATHODE 2. ANODE 3. GATE 4. ANODE
STYLE 5:
PIN 1. GATE 2. ANODE 3. CATHODE 4. ANODE STYLE 6:
PIN 1. MT1 2. MT2 3. GATE 4. MT2
STYLE 7:
PIN 1. GATE 2. COLLECTOR 3. EMITTER 4. COLLECTOR
1 2 3 4
STYLE 8:
PIN 1. N/C 2. CATHODE 3. ANODE 4. CATHODE
STYLE 9:
PIN 1. ANODE 2. CATHODE 3. RESISTOR ADJUST 4. CATHODE
STYLE 10:
PIN 1. CATHODE 2. ANODE 3. CATHODE 4. ANODE
b D E
b3
L3
L4 b2
0.005 (0.13)M C
c2 A
c
C
Z
DIM MIN MAX MIN MAX MILLIMETERS INCHES
D 0.235 0.245 5.97 6.22 E 0.250 0.265 6.35 6.73 A 0.086 0.094 2.18 2.38 b 0.025 0.035 0.63 0.89
c2 0.018 0.024 0.46 0.61 b2 0.028 0.045 0.72 1.14 c 0.018 0.024 0.46 0.61
e 0.090 BSC 2.29 BSC b3 0.180 0.215 4.57 5.46
L4 −−− 0.040 −−− 1.01 L 0.055 0.070 1.40 1.78
L3 0.035 0.050 0.89 1.27
Z 0.155 −−− 3.93 −−−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI- MENSIONS b3, L3 and Z.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUM PLANE H.
7. OPTIONAL MOLD FEATURE.
1 2 3
4
XXXXXX = Device Code A = Assembly Location
L = Wafer Lot
Y = Year
WW = Work Week
G = Pb−Free Package AYWW XXX XXXXXG XXXXXXG
ALYWW
Discrete IC
5.80 0.228
2.58 0.102
1.60 0.063 6.20
0.244
3.00 0.118
6.17 0.243
ǒ
inchesmmǓ
SCALE 3:1
GENERIC MARKING DIAGRAM*
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
H 0.370 0.410 9.40 10.41 A1 0.000 0.005 0.00 0.13
L1 0.114 REF 2.90 REF L2 0.020 BSC 0.51 BSC
A1
H
DETAIL A
SEATING PLANE
A
B
C
L1 L
H L2GAUGEPLANE
DETAIL A
ROTATED 90 CW5
e BOTTOM VIEW
Z
BOTTOM VIEW SIDE VIEW
TOP VIEW
ALTERNATE CONSTRUCTIONS NOTE 7
Z
*This information is generic. Please refer to device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking.
98AON10527D DOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1 DPAK (SINGLE GAUGE)
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PUBLICATION ORDERING INFORMATION
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Voice Mail: 1 800−282−9855 Toll Free USA/Canada Phone: 011 421 33 790 2910
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For additional information, please contact your local Sales Representative
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