Microsoft PowerPoint - (080710)福岡チャプター発表

More than Mooreの展望：

３次元集積のためのチップ間無線接続技術

黒田忠広

慶應義塾大学教授

IEEE Fellow, IEEE SSCS AdCom, Distinguished Lecturer

IEEE CAS Fukuoka Chapter講演会 (2008/7/10)

Silicon Age

„

Oil Shock（1973）:

From Iron Age to Si Age

From Energy Age to Information Age

LSI (

Si

) : Computing

Fiber Optics (

Si

O

₂

): Communication

Year

10000

1000

1960

1970

1980

1990

100

10

2000

Oil

Iron

Si

Oil Shock

Energy Age

Iron Age

Information Age

Si Age

Normalized in 1973

Si

Moonlight Project: Energy Saving

Sunshine Project: Alternate Energy

More Moore and More than Moore

„

End of Moore’s Law?（2003）:

More Moore : Further Scaling (SoC)

More than Moore : 3D Integration (SiP)

CPU

SRAM

_D

R

A

M

Analog

CPU

SRAM

_D

R

A

M

Analog

SoC (More Moore)

D

R

AM

Flash

Analog

CPU

D

R

AM

Flash

Analog

CPU

D

R

AM

Flash

Analog

CPU

SiP (More than Moore)

Wireless Chip Links

D

R

A

M

PC Board

Package

PCB

D

R

A

M

SRAM

Analog

CPU

Connection

D

R

A

M

PC Board

Package

PCB

D

R

A

M

SRAM

Analog

CPU

Connection

From SoC to SiP

System-on-a-Board

Lower Cost, QT

_AT

Low pow

er, High s

_peed

System-in-a-Package (SiP)

System-on-a-Chip (SoC)

Mask Set Cost [M$]

0 0.5 1 1.5 2 2.5 0.4 0.25 0.2 0.18 0.15 0.13 90n 65n 0 0.5 1 1.5 2 2.5 0.4 0.25 0.2 0.18 0.15 0.13 90n 65n 0 0.5 1 1.5 2 2.5 0.4 0.25 0.2 0.18 0.15 0.13 90n 65n

µm]

CANDE 2010 Prediction

CANDE 5-Year predictions from 2005 (to be reviewed in 2010) were:

1) IC-Package CAD will be a part of standard design flow

2) India and China will have more EDA startups than U.S.

3) Analog Designers will still resist high-level models and

languages

4) A complete Open Source RTL-GDS tool flow will exist

5) Nearly all EDA tools will take advantage of multi-processors

6) Fewer than 200 commercial chips released in 45 nm technology

7) No practical nanotech computing products

8) SPICE-type simulators will still be the workhorse of analog

designs

9) Moore's law will be dead

10) System in Package will boom

The

CANDE （Computer-Aided Network DEsign）

Committee is a technical activity of the

IEEE Circuits and Systems Society and IEEE Council on Electronic Design Automation

which acts as a working group for electronic computer-aided design. The first CANDE

Workshop was held in 1972, organized by Steve Director.

Past Results of CANDE Prediction

CANDE PREDICTIONS – as rated at the 2001 CANDE Workshop

Results

: 19 came true

, 4 partially

, 15 did not

Key:

Blue – Correct (not necessarily in 5 years)

Green – Did occur partially

Red – Did not occur

○ 1. UNIX will be the dominant operating system

× 2. General Purpose Parallel machines will replace today’s computers; they will be designed for high performance on major CAD algorithms (e.g. SPICE, Logic Synthesis, Fault Simulation, Simulated Annealing, Device Simulation)

△ 3. The big problem for CAD will become the validation of specifications

× 4. The major developments in CAE/CAD will be in the environments for users

○ 5. The test problem will still be considered NP-hard, boring, and unsolved ○ 6. Many CAD tools will finally use hierarchy effectively

× 7. General silicon compiler not developed yet but targeted silicon compiler for DSP and other specific applications will be in general use

○ 8. SPICE will still be the standard circuit simulator

○ 9. CAD Tools will increasingly take into account statistical fluctuations in the manufacturing process

○ 10. Full hand-crafted custom will still be an important part of design

1979 (4 came true, 1 partially, 3 did not)

× 1. Design System will be a Network Formed With Dedicated Processors For Specific Functions

× 2. Heavy Emphasis on Testability and Test Generation During the Design Phase

○ 3. Integrated Verification Tools for Checking at Each Step in the Design Cycle ○ 4. Much Greater Use of Canonical Circuit Forms (PLA, ROM) Via Design Aids ○ 5. The Design Station is Highly Interactive for all Phases and Includes Graphics

△ 6. Sets of Compatible Software will be Used for Design and Verification

△ 7. Circuit and Process Simulation Programs are Closely Linked to an Ongoing Process Data Storage System

× 8. Layout will be Manipulated in Symbolic Form

1996 (4 came true, 1 partially, 5 did not)

× 1. Windows NT will be the only OS for commercially viable CAD applications × 2. X86 machines will ship as more than 50% of EDA platforms

× 3. More than 80% of the CAD effort will be directed toward software and “FPGA”-based programmable hardware

○ 4. EDA companies will distribute all their products (tools, libraries, etc,) on the Internet

△ 5. The hardware/software co-design problem will have become the driving system-level problem

× 6. “Pay per use” EDA tools will be in widespread use

○ 7. Tool suites for mainstream designers will be a significant fraction of total EDA ○ 8. Portable voltage will be 1.8 – 1.2 V, driving significant new circuit design and EDA

challenges

× 9. The IP crisis will be solved by an open IP industry and a mix-and-match standard

○ 10. Software will have become 60 to 80 % of the overall cost of an embedded system

1991 (5 came true, 1 partially, 4 did not)

○ 1. Hardware/software co-design will be one of the most important design problems ○ 2. Support will still be the biggest hidden cost for both CAD vendors and customers

× 3. MCM CAD becomes a reality

×4.MCM will enable new CAD and semiconductor businesses

△ 5. Internal CAD will make a come-back

○ 6. There will be tools for validation of specifications

× 7. Partitioning will emerge as a commercial product

○ 8. The telecommunications industry will provide the most challenging problems in CAD ○ 9. SPICE algorithms still dominate circuit simulation

Chip Stacking and Wire Bonding in SiP

0

2

4

6

8

10

標準（polishなし）

Polish

Non-polished

Si chip backside

Polished

Si chip backside

Si

chip

tran

sverse ruptun

e

s

tren

gth

Si chip

Strength improved

by polishing

300mmφ 25um wafer （Polished)

Bottom die

Top die

Die-to-die bond

(stud bump/reverse bond)

Cross wire

bond

Cross wire

bond

Bond on

overhang die

Pre-Verification by Simulation

Memory Bus

Chip Performance and Pin Bandwidth

Chip Performance

Year

70

80

90

00

10

X1

.7

0

/ y

ea

r

100

MIPS [instruction/s]

0.01

0.1

1

10

1000

10000

100000

1000000

Pin Bandwidth

Data Rate [MB/s]

1

10

10

0

1000

10000

Bus on Board

ATA

(HDD)

Ethernet

X1

.4

4

/ y

ea

r

The Gap Is Caused by Topological Difference

TRANSISTOR

Scaling

Per year

Gate length

[

x]

0.87

Voltage

[

V]

0.87

Capacitance

[c]~[

x

2

_/

x]

_0.87

Current

[

i]~[v

2

_/

x]

_0.87

Speed

[

i/cv]

1.15

WIRE

Wire pitch

[

x]

0.87

Chip size

[

s]

1.06

Tracks

[

t]~[s/x]

1.22

Grids

[

g]~[t

2

_]

_1.49

„

Rent’s rule:

Bandwidth demand from a module with

capacity C (grids*speed) grows as C

0.7

_.

Required pin bandwidth: x1.45/year

„Pin bandwidth

1.15 (Speed) x 1.11 (Pin #) = x1.28/year

Periphery

„Chip performance

1.15 (Speed) x 1.49 (Grids) = x1.71/year

Area

„

Moore’s Law

Ch

ip

p

er

fo

rm

an

ce

:

1.

71

/y

ea

r

Pin

ba

nd

wi

dth

: 1

.45

/ye

ar

Scaling:1

.28/year

circuit

innovation

Year

Data Rate

Challenges in Wireline Link

’96

’98

’00

’02

’04

’06

100G

1T

Data Ra

te [b/s]

Year

’

’

’

’

’

’

’

’

’

’

’

’

’

’

’

’

’

’

1G

10G

Speed-wall

Stanford (1ch)

Stanford (1ch)

NEC (1ch)

Power/Area-wall

Toshiba

(4ch,4W)

Rambus

(26ch)

NTT

(16ch,8W)

Hotrail

(32ch)

NEC (4ch,5W)

NEC (21ch,3W)

NEC (20ch,8W)

TI (20ch,6W)

Intel (32ch,15W)

IBM,Sony,

Toshiba (48ch,6W)

Hitachi

(1024ch,12W)

From Line to Area

MPU

Memories

Sensor / RF / Analog

„

Bonding (Conv.)

„

Through Si Via (Future)

(+) area contact：

large # of connections（~10000）

short distance（~0.1mm）

(-) expensive process / reliability issue

(-) low yield due to Known Good Die

issue : difficult to test in fine pitch

(-) scaling limit due to mechanical

contacts （~10

µm pitch）

(+) low cost, practical

(-) peripheral contact：

small # of connections

（~100）

From Mechanical to Electrical

„

TSV

„

Wireless Interface

„

Proposal

wireless transceiver arrays

(-) process

(-) KGD

(-) scaling limit

(+) no addition in process, no reliability issue

(+) KGD solvable : easy to attach and remove

(+) high density channels (below 10

µm pitch)

(+) 3D scaling scenario (thinning a chip)

(+) channels through active devices

Distance and Frequency

50G

50M

50k

1

µm

1mm

1m

1km

Communication Distance:

x

Signal Frequency:

f

[Hz]

RFID

(135kHz)

RFID

(13.56MHz)

mm-Wave

Cellular

FM

RFID

(2.4MHz)

WLAN

f = c/(2

π

x)

Reactive (Near Field)

Radiative (Far Field)

■

■

Chip-link

through Package

Chip-link

in SiP

0.01

0.1

1

10

100

1000

-240

-220

-200

-180

-160

-140

-120

-100

-80

-60

-40

-20

0

Received signal strength (a.u.)

Distance(mm)

Coupling Mode

x

/

1

∝

3

/

1 x

V

_RX

∝

RX loop

TX loop

Distance x

r = 0.1mm

f = 1GHz

π

λ 2

/

Reactive

Radiative

TX

TX

RX

TX

RX

TX

o

RX

j

ω

I

x

r

r

r

n

n

πµ

V

⋅

⎟

⎠

⎞

⎜

⎝

⎛

₊

=

3

2

2

2

2

2

@ reactive region

r = 0.1mm

-60dB/dec

-20dB/dec

Magnetic Field of Reactive Region

r = 0.5mm

f = 1GHz

Magnetic field strength (z-axis component) in yz (x=0) plane

mm

π

λ

/

2

≈

50

x

y

z

4 mm

Magnetic Field of Reactive Region

r = 0.5mm

f = 1GHz

x

y

z

Magnetic field strength (z-axis component) in xy (z=0.5mm) plane

mm

π

λ

/

2

≈

50

8 mm

Magnetic Field of Radiative Region

r = 0.5mm

f = 100GHz

Magnetic field strength (z-axis component) in yz (x=0) plane

mm

π

λ

/

2

≈

0

.

5

x

y

z

8 mm

Magnetic Field of Radiative Region

r = 0.5mm

f = 100GHz

x

y

z

Magnetic field strength (z-axis component) in xy (z=0.5mm) plane

mm

π

λ

/

2

≈

0

.

5

Reactive Proximity Communication

„

Received signal rapidly decays at distance

longer than antenna size

†

Suitable for dense channel arrangement (small cross talk)

Area Interface for 3D Integration

Capacitive

Coupling

[3]

Wired

Wireless

2 Chips

(Face-to-Face)

Over 3 Chips

(Face up/dn)

Inductive

Coupling

[4]

Micro-Bump

[1]

Inductive vs. Capacitive

Capacitive

Coupling

[3]

Wired

Wireless

2 C

h

ips

(Fac

e

-to

-Face

)

Ov

er

3 Ch

ip

s

(Fac

e u

p

/dn

)

Inductive

Coupling

[4]

Micro-Bump

[1]

Through-Si Via

[2]

Capacitive

Coupling

[3]

Wired

Wireless

2 C

h

ips

(Fac

e

-to

-Face

)

Ov

er

3 Ch

ip

s

(Fac

e u

p

/dn

)

Inductive

Coupling

[4]

Micro-Bump

[1]

Through-Si Via

[2]

Capacitive

Coupling

[3]

Wired

Wireless

2 C

h

ips

(Fac

e

-to

-Face

)

Ov

er

3 Ch

ip

s

(Fac

e u

p

/dn

)

Inductive

Coupling

[4]

Micro-Bump

[1]

Through-Si Via

[2]

Capacitive

Coupling

[3]

Wired

Wireless

2 C

h

ips

(Fac

e

-to

-Face

)

Ov

er

3 Ch

ip

s

(Fac

e u

p

/dn

)

Inductive

Coupling

[4]

Micro-Bump

[1]

Through-Si Via

[2]

Capacitive-Coupling Link

[8] CICC’03, Sun Microsystems

„

Chip to Chip

[5] CICC’02, NC State Univ.

[6] ISSCC’05, NC State Univ.

„

Chip to Interposer

substrate

IC #1

IC #2

Trench

Interconnection layer

DC connection

(Solder bump)

AC connections DC connection

(Solder bump)

substrate

IC #1

Trench

Interconnection layer

DC connection

(Solder bump)

AC connections

DC connection

(Solder bump)

2µm

[3] ISSCC’03, Univ. Tokyo and Keio Univ.

Base chip

Face-down chips

30um pitch mini-pads

(Top metal layer)

1µm

Chip 1

Chip 2

Chip 3

Txdata Rxdata

Txdata

Rxdata

Chip 1

Chip 2

Inductive-Coupling Link

+

+

Digital CMOS Circuits

Multi-layer Wires

ISSCC 2006

(1Tbps)

ISSCC 2005

(200Gbps)

ISSCC 2004

(1Gbps)

Transmitter Chip (Top) 1024ch Data Transceivers Receiver Chip (Bottom)

Clock Transceivers BI ST Clo ck C o n tro l DC Probe for Top Chip 195 Transceiv er Channel Array AC Probefor Bottom Chip for Bottom Chip AC Probe DC Probe Bond in g Wires for Bottom Chip Bond in g Wires for T op C h ip Tx Array Rx Array Bottom Chip Top Chip Inductor TEG

ISSCC 2007

(140fJ/b)

ISSCC 2008

(11Gbps/ch)

D=60

µm

D=60

µm

Inductive vs. Capacitive: Loss by Body

0

0.2

0.4

0.6

0.8

1

Normalized S21

Resistivity,

ρ [Ωcm]

10

₁₀

₁₀

₁₀

₁₀

₁₀

₁₀

₁₀

₁₀

_∞

@10GHz

~ ~

~ ~

Loss=exp(-

T

ωµ 2

_/

ρ

) [12]

Typical

In

d

u

c

tiv

e

C

a

p

a

c

it

iv

e

Inductor

Si

Capacitor

T=60

µm

Charge

Eddy

„

Capacitive: only for 2 chips, placed face-to-face

Inductive vs. Capacitive: Package Flexibility

Bed

Face-up Chip

Face-up Chip

Face-up Chip

Face-up Chip

Bed

Face-up (Logic)

Face-down (Memory)

Cavity

Bed

Face-down (Logic)

Face-up (Memory)

Inductive Coupling

Capacitive Coupling

[7]

„

_{Inductive: compatible with}

conventional wire/area bonding

„

Capacitive: need new

Inductive vs. Capacitive: Range Scalability

Lower Limits by Comparator

Normalized S21

Communication Distance

X

1

1

µm

10

µm

100

µm

1mm

10mm

10

-2

10

-4

10

-6

10

-8

Inductive

Capacitive

Si

Si

6

µm

X

6

µm

D

10µ

_m

10

_0µ

m

D

=1

_m

m

D

=

1m

m

10

0µ

_m

10µ

_m

D

Inductive vs. Capacitive: Device Scalability

„

Coupling coefficient is enlarged

by increasing # of metal layers.

„

Transmission power can be

secured even at low

V

_DD

’s.

0.2

0.4

0.6

0.8

1

0.2

0.4

0.6

0.8

1

1.2

Normalized Transmission Power

Inductive

Capacitive

V

+

-I

V

V

V

V

1

3

5

7

9

11

13

3

4

5

6

7

8

9

10

15

Normalized S21

Inductive

Capacitive

Tx

Rx

10

µm

2

µm

C

Inductive vs. TSV,

µ-bump

Capacitive

Coupling

[3]

Wired

Wireless

2 C

h

ips

(Fa

c

e

-to

-Fa

ce

)

Ov

er

3 C

h

ips

(F

ac

e u

p

/dn

)

Inductive

Coupling

[4]

Micro-Bump

[1]

Through-Si Via

[2]

Capacitive

Coupling

[3]

Wired

Wireless

2 C

h

ips

(Fa

c

e

-to

-Fa

ce

)

Ov

er

3 C

h

ips

(F

ac

e u

p

/dn

)

Inductive

Coupling

[4]

Micro-Bump

[1]

Through-Si Via

[2]

Capacitive

Coupling

[3]

Wired

Wireless

2 C

h

ips

(Fa

c

e

-to

-Fa

ce

)

Ov

er

3 C

h

ips

(F

ac

e u

p

/dn

)

Inductive

Coupling

[4]

Micro-Bump

[1]

Through-Si Via

[2]

Capacitive

Coupling

[3]

Wired

Wireless

2 C

h

ips

(Fa

c

e

-to

-Fa

ce

)

Ov

er

3 C

h

ips

(F

ac

e u

p

/dn

)

Inductive

Coupling

[4]

Micro-Bump

[1]

Through-Si Via

[2]

LAN Wire vs. Wireless

path loss

multi-path fading

Multiple access in free space:

cell, TDMA, FDMA, CDMA

Wired LAN (Ethernet)

Wireless LAN (WiFi)

802.3u（100BASE-T）

802.11b

twisted pair

2.4GHz

<100m

<100m

Data rate

High speed

(100Mbps)

Low speed (11Mbps)

Reliability

High

(BER<10

-14

₎

_{Low (BER~10}

-4

₎

Cost

Inexpensive

(~$15)

Expensive (~$100)

Power

Low

(~100mA)

High (~400mA)

Size

Small

Large (w/ antenna)

Connection

Easy

(plug and play)

Complex (authentication)

Usability

Messy/Difficult (ie.wall)

Neat, Simple, Easy

Mobility

Low/Immobile

Movable

path loss

multi-path fading

multi-path fading

Multiple access in free space:

cell, TDMA, FDMA, CDMA

Wired LAN (Ethernet)

Wireless LAN (WiFi)

802.3u（100BASE-T）

802.11b

twisted pair

2.4GHz

<100m

<100m

Data rate

High speed

(100Mbps)

Low speed (11Mbps)

Reliability

High

(BER<10

-14

₎

_{Low (BER~10}

-4

₎

Cost

Inexpensive

(~$15)

Expensive (~$100)

Power

Low

(~100mA)

High (~400mA)

Size

Small

Large (w/ antenna)

Connection

Easy

(plug and play)

Complex (authentication)

Usability

Messy/Difficult (ie.wall)

Neat, Simple, Easy

Inter-Chip 3D Link Wire vs. Wireless

Wired Inter-Chip Link

Wireless Inter-Chip Link

Micro-bump (2 chips)

Capacitive coupling (2 chips)

TSV ( >3 chips)

Inductive coupling (>3 chips)

<100

µm

<100

µm

Data rate

High speed

Low speed

?

Reliability

High-reliable

Low-reliable

?

Cost

Inexpensive Expensive

?

Power

Low

High

?

Size

Small

Large (w/ Antenna)

?

Connection Easy (plug on play)

Complex (authentication)

?

Usability

Messy/Difficult (ie.wall) Neat, Simple, Easy

?

Mobility

Low/Immobile

Movable

?

100

µm: 0.001 wave length (proximity)

100m ：1000 wave length

Wired Inter-Chip Link

Wireless Inter-Chip Link

Micro-bump (2 chips)

Capacitive coupling (2 chips)

TSV ( >3 chips)

Inductive coupling (>3 chips)

<100

µm

<100

µm

Data rate

High speed

Low speed

?

Reliability

High-reliable

Low-reliable

?

Cost

Inexpensive Expensive

?

Power

Low

High

?

Size

Small

Large (w/ Antenna)

?

Connection Easy (plug on play)

Complex (authentication)

?

Usability

Messy/Difficult (ie.wall) Neat, Simple, Easy

?

Mobility

Low/Immobile

Movable

?

100

µm: 0.001 wave length (proximity)

100m ：1000 wave length

World Fastest (1Tb/s) Data Rate

Data Rate [b/s]

’96

1G

10G

100G

1T

Year

’98

’00

’02

’04

’06

Hitachi (1024ch, 12W)

NEC (4ch, 5W)

NEC (21ch, 5W)

NEC (20ch, 8W)

TI (20ch 6W)

NTT

(16ch, 8W)

Intel (32ch, 15W)

Toshiba (4ch, 4W)

Rambus (26ch)

Hotrail

(32ch)

Sony (1300ch), TeraChip (16ch,

15W)

Rambus FlexIO

(48ch, 6W)

Power/Area Wall

NEC (1ch)

Stanford (1ch)

Stanford (1ch)

Keio

(1Gb/s/ch, 1024ch, 3W)

Keio (1ch, 46mW)

Keio (195ch, 1.2W)

Speed Wall

Maximum Data Rate per Channel

0

-0.2

0.2

V

[V]

0

-0.2

0.2

V

[V]

I

C

L

R

/2

k

V

C

L

R

/2

R

/2

R

/2

X

D=X

Time [ns]

0

4

8

12

16

Time [ns]

0

4

8

12

16

0

-0.2

0.2

V

[V]

0

-0.2

0.2

V

[V]

Communication Distance,

X [

µm]

0.1

1

10

100

1000

0

20

40

60

80

100

120

Maximum Data Rate [Gb/s]

f

= 1/2

π LC

f

/3

[14]

[10]

[10]

Burst Data Transmission at 11Gb/s

1UI=156ps @ 6.4Gb/s

0

39

78

117

156

t

[ps]

t

t

Timing

Variation

<13%UI

400M

b/

s

Lt

xdat

a

[1

5:

0]

System

Clk

Reset

Stop

Txdata

6.4Gb/s Data

Burst Mode

8:1 MUX

2:1 MUX

Tx

Rx

Rx

Data Link

Clock Link

Tx

Ch

ip

Rx

Chi

p

Tx

Txdata

Inductor

Source

Synchronous

3.2GHz Local OSC

Counter

St

op

400MHz

System Clk

Reset

Txclk

8:1 MUX

8

8

1:8 DEMUX

1:2 DEMUX

Rxdata

_{1:8 DEMUX}

8

8

400M

b/

s

Lrxdat

a

[1

5:

0]

Rxclk

t

T: 0~60ºC

V

: 10%

P: FF~SS

Buffer

1UI=156ps @ 6.4Gb/s

0

39

78

117

156

t

[ps]

t

t

Timing

Variation

<13%UI

400M

b/

s

Lt

xdat

a

[1

5:

0]

System

Clk

Reset

Stop

Txdata

6.4Gb/s Data

Burst Mode

System

Clk

Reset

Stop

Txdata

6.4Gb/s Data

Burst Mode

8:1 MUX

2:1 MUX

Tx

Rx

Rx

Data Link

Clock Link

Tx

Ch

ip

Rx

Chi

p

Tx

Txdata

Inductor

Source

Synchronous

3.2GHz Local OSC

Counter

St

op

400MHz

System Clk

Reset

Txclk

8:1 MUX

8

8

1:8 DEMUX

1:2 DEMUX

Rxdata

_{1:8 DEMUX}

8

8

400M

b/

s

Lrxdat

a

[1

5:

0]

Rxclk

t

T: 0~60ºC

V

: 10%

P: FF~SS

Buffer

Asynchronous Transceiver

V

_R

V

_B

+

-Rxdata

I

_T

Txdata

Txdata

Rxdata

Transmitter

Txdata

[V]

I

T

[mA]

V

R

[mV]

1.5

Rxdata

[V]

0

0.5

1

1.5

Latency=36ps (<0.5FO4)

-1.5

4

-4

100

-100

0.5

-0.5

0

0

0

0

Performance Comparison

0

2.5

5

7.5

10

12.5

0

10

20

30

40

50

This Work

_UCLA

Inductive

Capacitive

11Gb/s

11Gb/s

0.39pJ/b

3

µm

0.015mm

_0.016mm

Pulse

25GHz ASK

180nm CMOS 130nm CMOS

<10

_1.02x10

Interconnect

Data Rate

Energy

Distance

Channel Area

Modulation

Process

BER

1.4pJ/b

15

µm

Data Ra

te [Gb/s]

Communication Distance [

µm]

_UCLA

This Work

Capacitive

Inductive

World Lowest Energy (0.14pJ/b)

Energy Dissipation [pJ/b]

Year

Rambus

(90nm)

Inductive Coupling (180nm)

Inductive Coupling (90nm)

[20.2] “A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with

Digitally-Controlled Precise Pulse Shaping”

Inductive

µ-bump

w/ interposer

Wire Bonding

2mW

20mW

200mW

HDTV

H.264/AVC

(23.1Gb/s)

Energy Reduction

2

CV

E

_RX

=

2

pulse

T

TX

QV

Idt

V

V

T

E

⋅

∝

⋅

=

=

∫

.

const

t

I

=

∂

∂

scale as CMOS gate

shorten pulse width (timing issue)

lower voltage

Tx.data

2.2pJ/b

Rx.data

0.6pJ/b

180nm

1.8V

2.8pJ/bit

90nm

1.0V

0.14pJ/bit

0.11pJ/b

0.03pJ/b

v

t

T

i

tt

QV

E

CV

Q

=

=

World Smallest (1mm

2

/Tb/s)

■ Horizontal Size

Inductive: 30µm pitch -> 20µm pitch

incl. transceiver circuits

TSV/µ-bump:

need additional area for circuits

difficult to scale due to ESD

Tx

Rx

100

1k

10k

100k

10

1

Layout Area / Data Rate

[mm

2

/Tb/s]

Year

’96

’98

’00

’02

’04

’06

Sony

µ-bump

TI

NEC

Intel

NEC

NEC

Hotrail

Hitachi

NTT

Toshiba

IBM,Sony,

Toshiba

Keio

(1024ch)

Keio

(195ch)

Keio

(1ch)

Upper TSV

Lower TSV

Cu Bump

SiO

Resin

■ Vertical Size

Inductive: no bump, thinner packaging

TSV/Bump: need bump, thicker

Channel Pitch vs. Crosstalk

X

Inductor Array

Y

D

-22.5

-17.5

-12.5

-7.5

-2.5

1

2

3

4

BER=10

-12

X

=D

5

Interference-to-Signal Ratio (ISR) [dB]

Y/D

Channel Pitch

Y [

µm]

120

240

360 480600 840

1200

10

10

10

10

1

Normalized Crosstalk

1/Y

₃

Slo

pe

X

=D

Narrower Pitch by Time Interleaving

-50

0

50

-50

0

50

-50

0

50

0

1

2

3

Received Voltage [mV]

Crosstalk

Signal

50mV

25mV

10mV

w/o

Time Interleaving

2-phase

Time Interleaving

4-phase

Time Interleaving

Ch Array

[14] ISSCC’06, Keio Univ.

[10] ISSCC’05, Keio Univ.

As Reliable As Wireline (BER<10

-13

₎

10

10

10

10

∆

T [ps]

Bit Error Rate

300

350

250

400

1Gb/s

φ

φ

Data Tx

Data Rx

Rxdata

Txdata

2

_{-1 PRBS}

Generator

Txclk

Clk Tx

Clk Rx

Error

Counter

∆

T

Rxclk

1GHz Clock

10

10

10

10

10

10

10

・Easy to synchronize

[14] ISSCC’06, Keio Univ.

BST TYP

WST

11ps

10ps

Skew=

8ps

Timing

Margin=130ps

Misalignment Tolerance

・3µm alignment error can be compensated by 5% power increase.

0

5

10

15

-5

-10

-15

Misalignment,

∆

Y,

∆

Z [

µm]

Normalized (

V

–

V

)

Rx Channel

X=15

µm

P~30

µm

Tx Array

Z

Y

D~30

µm

Tim

e I

_nt

er

_le

av

in

_g

Sin

gle

_C

ha

_nn

el

(V

=0

)

0.25

0.5

0.75

1

+3

µm

Stacked Chips

Alignment

Mark

Misalignment

<3

µm

Interference Immunity

„

Interference to circuits:

negligibly small for digital

„

Interference from environment:

negligibly small for receiver

diminishing by scaling

1

10

100

1000

10000

100000

10k

1M

100M

10G

100G

0.00001

0.0001

0.001

0.01

0.1

1

10

1G

10M

100k

Frequency [Hz]

Magnetic Field Integrity,

B

[m

G]

Noise,

V

[m

V]

D=60

µm

RX

B

V

B

(Regulation)

-30

-20

-10

0

10

20

30

-60

-45

-30

-15

0

15

30

45

60

Position,

Y [

µm]

Noise Voltage [

m

V]

D=60

µm

TX

Y

I

5mA

125ps

M2

M1

1mm

S

ig

na

l L

in

e

Shielding by Power Lines

Rx Chip

Tx Chip

Technology : 65nm CMOS

Stacked Chip Microphotograph

D=80

µm

D=160

µm

L&S(II)

50%

L&S(II)

16%

L&S(I)

16%

Mesh

16%

Mesh

39%

L&S(II)

50%

L&S(II)

16%

L&S(I)

16%

*L&S : Line and Space

Lower : Metal density [%]

Tx Inductor

D=160

µm

240

µm

240

µm

Rx Inductor

70

µm

Tx Inductor

D=160

µm

240

µm

240

µm

Rx Inductor

70

µm

Rx Inductor

D=80,160

µm

Measurement Result (Power Lines)

50

0

₁₀

₂₀

₃₀

₄₀

50

0

₁₀

₂₀

₃₀

₄₀

Required Normalized Transmit Power

Metal Density [%] (240

µm Square Area)

1

1.75

1.5

2

_{BER = 10}

_{BER = 10}

-8

-8

_{, 1Gbps}

1.25

D=160

µm

D=80

µm

Measured

Mesh Type

Line and Space (I)

Line and Space (II)

Si

m

ul

at

Interference from Signal Lines

Rx Chip

Tx Chip

Tx/Rx

Inductor

Signal Line

(Red Line)

3 mm

3 mm

250MHz

Under Rx

Inductor

Rx

Tx

3 mm

Under Tx

Inductor

Signal

Noise

160

µm

3 mA

V

_Tx

>1V

V

_Rx

<50mV

Measurement Result (Signal Lines)

Timing of Data Transition in Signal Line,

∆T [ns]

Timing of Data Transition in Signal Line,

∆T [ns]

BER = 10

-8

-1.0

-0.6

-0.2

+0.2

+0.6

+1.0

1.1

0.0

-0.4

-0.8

+0.4

+0.8

Data Rate : 250 Mbps

∆

T

Diameter of inductor : 160

µm

-1.0

-0.6

-0.2

+0.2

+0.6

+1.0

1

1.05

0.0

-0.4

-0.8

+0.4

+0.8

∆

T

Under Tx

Inductor

Rx

Tx

Rx

Tx

Under Rx

Inductor

Worst Timing

V

_R

V

_Rxclk

V

_noise

Rx

Interference to SRAM

Measured SRAM Cell

Bit Line

Transmitter Circuit

90

µm

90

µm

SRAM Array

(Meshed)

65nm CMOS

Measurement Result (SRAM)

Supply Voltage :

V

[V]

1.4

0.6 0.65

0.8

1.0

Typical

Range

1.2

w/o

Inductive-Coupling Link

(dotted line)

w/

Inductive-Coupling Link

(solid line)

Erro

r R

a

te

in

R

ead

O

p

er

at

ion

o

f

SRA

M

10

-12

10

-0

10

-3

10

-6

10

-9

Supply Voltage :

V

[V]

1.4

0.6 0.65

0.8

1.0

Typical

Range

1.2

w/o

Inductive-Coupling Link

(dotted line)

w/

Inductive-Coupling Link

(solid line)

Erro

r R

a

te

in

R

ead

O

p

er

at

ion

o

f

SRA

M

10

-12

10

-0

10

-3

10

-6

10

-9

Cost

Inductive

TSV,

µ-bump

Process

Standard CMOS

New development

ESD protection

No need

Need

AC Coupling

・No need for level shifters under different

V

_DD

’s

・No need for additional

V

_DD

’s nor thick gate oxide transistors

・

_V

_DD

_{’s can change: in burn-in, dynamic voltage scaling}

Rx

Tx

1V

2V

Txdata

Rxdata

Txdata

1V

2V

2V

2V

Rxdata

Chip2,

V

_DD

=2V

Chip1,

V

_DD

=1V

Detachable

・ At-speed test possible if same transceiver

are arranged in test head:

solve KGD problem

improve yield

remove built-in test circuit

・ Wafer entirely test possible:

reduce test time and cost (￠3 /min)

・ Avoid Pad damage by probe:

raise yield

・ Replace a high-speed connector:

improve reliability

reduce cost

Attainable Communication Distance

Only Comp.

Amp. + Comp.

(30dB)

Detectable level

Noise floor

10

-8

10

-6

10

-4

10

-2

1

10

µm

100

µm

1mm

10mm

Coupling Coefficient

Communication Distance

X

D

X

D=10

µm D=100µm D=1mm

Target

Magnetic Field Strength

0.01

0.1

1

10

Magnetic Field [dB a.u.]

D

λ = 60mm (f=5GHz)

λ/2π

-20dB/dec

(Radiative)

Distance

[mm]

-60dB/dec

(Reactive)

D = 0.1mm <<

λ/4

j

ω

I

x

r

r

r

n

n

πµ

V

⋅

⎟

⎠

⎞

⎜

⎝

⎛

₊

=

2

Antenna Size Dependence

Received Signal Strength [V]

0.01

0.1

1

10

D

10D

λ/2π

0.1mm

Distance

[mm]

+20 dB

+80dB

60dB

X10

1mm

j

ω

I

x

r

r

r

n

n

πµ

V

⋅

⎟

⎠

⎞

⎜

⎝

⎛

₊

=

2