第 9 章 Timer 69
10.2 制御レジスタ
10
Clock Generator
10.1 概要
クロックジェネレータは各モジュールに分配されるクロックの分周比を変更する．また，クロックゲーティグおよび ソフトウェアリセットを行う．
第10章 Clock Generator
表10.1: 各クロックラインのオフセット
0 CPU
1 Bus 2 SRAM
Main 0x000 3 Link Bus
4 DMAC 0 5 DMAC 1 6 DMAC 2 7 DMAC 3 0 Timer Bus 1 Timer 0
Timer 0x100 2 Timer 1
3 Timer 2 4 Timer 3 0 UART Bus
UART 0x200 1 UART 0
2 UART 1
GPIO 0x300 0 GPIO Bus
1 GPIO
SPI 0x400 0 SPI Bus
1 SPI
I2C 0x500 0 I2C Bus
1 I2C
0 PWM OUT Bus 1 PWM OUT 0 2 PWM OUT 1
PWM OUT 0x600 3 PWM OUT 2
4 PWM OUT 3 5 PWM OUT 4 6 PWM OUT 5 0 PWM IN Bus
PWM IN 0x700 1 PWM IN 0
2 PWM IN 1 0 Pulse Counter Bus Pulse Counter 0x800 1 Pulse Counter 0
2 Pulse Counter 1
PCI 0x900 0 PCI Bus
1 PCI Link IO Clock 0xa00 0 Link IO
Link SDRAM 2X Link SDRAM X2X
表10.2: リセットにおけるモジュールのオフセット
# オフセット
0 0x80
1 0x84
2 0x88
3 0x8c
4 0x90
5 0x94
6 0x98
7 0x9c
10.2.2 Clock Divider
Access : Read / Write Offset: 0x00
31 17
Reserved
16 T
15 0
Divider Ratio
16 Through Mode (T) Default: 0x0
このビットに1がセットされた場合，分周せずにPLLのクロックをスルーする（1/1分周）．
15:0 Divider Ratio Default: 0x0
nの値を書き込むと，PLLに対して2×(n+ 1)分周される．
10.2.3 Clock Gating
Access : Read / Write Offset: 0x04
31 G31
30 G30
29 G29
28 G28
27 G27
26 G26
25 G25
24 G24
23 G23
22 G22
21 G21
20 G20
19 G19
18 G18
17 G17
16 G16
15 G15
14 G14
13 G13
12 G12
11 G11
10 G10
9 G9
8 G8
7 G7
6 G6
5 G5
4 G4
3 G3
2 G2
1 G1
0 G0
n Gating #n(Gn) Default: 0x0
nビットに1がセットされた場合，#nのモジュールへのクロックの供給が停止される．nは表10.1の#の列の 数字である．
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第10章 Clock Generator
10.2.4 Reset
Access : Read / Write Offset: 0x80-0x9c
31 18
Reserved
17 R
16 A
15 0
Auto Reset Timer
17 Reset (R ) Default: 0x1
このビットに0がセットされた場合，モジュールにリセットをかける．1がセットされた場合，リセットを解除 する．
16 Auto Reset (A ) Default: 0x1
このビットに0がセットされた場合，オートリセットを有効にする．1がセットされた場合，オートリセットを 解除する．
15:0 Auto Reset Timer Default: 0x0
オートリセットが有効である場合，この値の間だけリセットがかかる．
11
Universal Asynchronous Receiver/Transmitter
初期アドレス: Channel0:0x30000000 Channel1:0x30000020
11.1 アドレスマップ
offset 31 24 23 16 15 8 7 0
0x0000 RB
0x0000 THR
0x0000 DL1
0x0004 IER
0x0004 DL2
0x0008 IIR
0x0008 FCR
0x000c LCR
0x00010 MCR
0x0014 LSR
0x0018 MSR
11.1.1 Receiver Buffer (RB) / Transmitter Holding Register (THR)
オフセット: 0x0000
7 0
bit名 機能
7-0 送信FIFOの入力および受信FIFOの出力．
11.1.2 Interrupt Enable Register (IER)
オフセット: 0x0004
第11章 Universal Asynchronous Receiver/Transmitter
7 4 3 2 1 0
bit名 機能
0 Received Data availble interrupt.
0 - Disabled.
1 - Enabled.
1 Transmitter Holding Register empty interrupt.
0 - Disabled.
1 - Enabled.
2 Receiver Line Status Interrupt.
0 - Disabled.
1 - Enabled.
3 Modem Status Interrupt.
0 - Disabled.
1 - Enabled.
7-4 Reserved. Should be logic 0 .
11.1.3 Interrupt Identification Register (IIR)
オフセット: 0x0008
7 6 5 4 3 1 0
0 When this is 0 , an interrupt is pending. When this is 1 , no interrupt is pending.
3-1 The following table displays the list of possible interrupts along with the bits they enable, priority, and their source and reset control.
Prio- Interrupt Interrupt Source Interrupt Reset
rity Type Control
011 1th Receiver Parity, Overrun or Reading the Line Line Framing errors or Status Register Status Break Interrupt
010 2nd Receiver FIFO trigger level FIFO drops below
Data reached trigger level
available
110 2nd Timeout There’s at least 1 Reading from the Indication character in the FIFO FIFO (Receiver
but no character has Buffer Register) been input to the
FIFO or read from it for the last 4
char times.
001 3rd Transmitter Transmitter Holding Writing to the Holding Register Empty Transmitter Holding
Register Register or reading
empty the IIR
000 4th Modem CTS, DSR, RI or Reading the Modem
Status DCD Status Register
5-4 Reserved. Should be logic 0 .
7-6 Reserved. Should be logic 1 for compatibility reason.
11.1.4 FIFO Control Register (FCR)
オフセット: 0x0008
7 6 5 3 2 1 0
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第11章 Universal Asynchronous Receiver/Transmitter
bit名 機能
0 Ignored(Used to enable FIFOs in NS16550D). Since this UART only supports FIFO mode, this bit is ignored.
1 Writing a 1 to bit 1 clears the Receiver FIFO and resets its logic. But it doesn t clear the shift register, i.e. receiving of the current character continues.
2 Writing a 1 to bit 2 clears the Transmitter FIFO and resets its logic. The shift register is not clreared, i.e. transmitting of the current character continues.
5-3 Ignored.
7-6 7-6 Define the Receiver FIFO Interrupt trigger level.
00 - 1 bytes 01 - 4 bytes 10 - 8 bytes 11 - 16 bytes
11.1.5 Line Control Register (LCR)
オフセット: 0x000c
7 6 5 4 3 2 1 0
1-0 Select number of bits in each character.
00 - 5 bits 01 - 6 bits 10 - 7 bits 11 - 8 bits
2 Specify the number of generated stop bits.
0 - 1 stop bit.
0 - 1.5 stop bits when 5-bit character length selected and 2 bits otherwise. Note that the receiver always checks the first stop bit only.
3 Parity Enable.
0 - No parity
1 - Parity bit is generated on each outgoing character and is checked on each incoming one.
4 Even Parity select.
0 - Odd number of 1 is transmitted and checked in each word (data and parity combined).
In other words, if the data has an even number of 1 in it, then the parity bit is 1 . 1 - Even number of 1 is transmitted in each word.
5 Stick Parity bit.
0 - Stick Parity disabled.
1 - If bits 3 and 4 are logic 1 , the parity bit is transmitted and checked as logic 0 . If bit 3 is 1 and bit 4 is 0 then the parity bit is transmitted and checked as 1 . 6 Break Control bit.
1 - The srial out is forced into logic 0 (break state).
0 - Break is disabled.
7 Divisor Latch Access bit.
1 - The divisor latches can be accessed.
0 - The normal registers are accessed.
11.1.6 Modem Control Register (MCR)
オフセット: 0x0010
7 5 4 3 2 1 0
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第11章 Universal Asynchronous Receiver/Transmitter
bit名 機能
0 Data Terminal Ready (DTR) signal control.
0 - DTR is 1 1 - DTR is 0
1 Request To Send (RTS) signal control 0 - RTS is 1
1 - RTS is 0
2 Out1. In loopback mode, connected Ring Indicator (RI) signal input.
3 Out2. In loopback mode, connected to Data Carrier Detect (DCD) input.
4 Loopback mode.
0 - normal operation.
1 - loopback mode. When in loopback mode, the Serial Output Signal (STX PAD O) is set to logic 1 . The signal of the transmitter shift register is internally connected to the input of the receiver shift register.
The following connections are made:
DTR→DSR RTS→ CTS Out1→RI Out2→DCD
7-5 Ignored.
11.1.7 Line Status Register (LSR)
オフセット: 0x0014
7 6 5 4 3 2 1 0
0 Data Ready (DR) indicator.
0 - No characters in the FIFO.
1 - At least one character has been received and is in the FIFO.
1 Overrun Error (OE) INDICATOR.
1 - If the FIFO is full and another character has been received in the receiver shift register.
If another character is starting to arrive, it will overwrite the data in the shift register but the FIFO will remain intact. The bit is cleared upon reading from the register. Generates Receiver Line Status interrupt.
0 - No overrun state.
2 Parity Error (PE) indicator.
1 - The character that is currently at the top of the FIFO has been received with parity error.
The bit is cleared upon reading from the register. Generate Receiver Line Status interrupt.
0 - No parity error in the current character.
3 Framing Error (FE) indicator.
1 - The received character at the top of the FIFO did not have a valid stop bit. The UART core tries re-synchronizing by assuming that the bit received was a start bit. Of course, generally, it might be that all the following data is corrupt. The bit is cleared upon reading from the register.
Generates Receiver Line Status interrupt.
0 - No framing error in the current character.
4 Break Interrupt (BI) indicator.
1 - A break condition has been reached in the current character. The break occurs when the line is held in logic 0 for a time of one character (start bit + data + parity + stop bit). In that case, one zero character enters the FIFO and the UART waits for a valid start bit to receive next character. The bit is cleared upon reading from the register. Generates Receiver Line Status interrupt.
0 - No break condition in the current character.
5 Transmit FIFO is empty.
1 - The transmitter FIFO is empty. Generates Transmitter Holding Register Empty interrupt.
The bit is cleared in the following cases: The LSR has been read, the IIR has been read or data has been written to the transmitter FIFO.
0 - Otherwise.
6 Transmitter Empty indicator.
1 - Both the transmitter FIFO and transmitter shift register are empty. The bit is cleared upon reading from the register or upon writing data to the transmit FIFO.
0 - Otherwise.
7 1 - At least one parity error, framing error or break indications have been received and are inside the FIFO. The bit is cleared upon reading from the register.
0 - Otherwise.
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第11章 Universal Asynchronous Receiver/Transmitter
11.1.8 Modem Status Register (MSR)
オフセット: 0x0018
7 6 5 4 3 2 1 0
bit名 機能
0 Delta Clear To Send (DCTS) indicator.
1 - The CTS line has changed its state.
1 Delta Data Set Ready (DDSR) indicator.
1 - The DSR line has changed its state.
2 Trailing Edge of Ring Indicator (TERI) detector. The RI line has changed its state from low to high state.
3 Delta Data Carrier Detect (DDCD) indicator.
1 - The DCD line has changed its state.
4 Complement of the CTS input or equals to RTS in loopback mode.
5 Complement of the DSR input or equals to DTR in loopback mode.
6 Complement of the RI input or equals to Out1 in loopback mode.
7 Complement of the DCD input or equals to Out2 in loopback mode.
11.1.9 Divisor Latches (DL)
オフセット: 0x0000(DL1), 0x0004(DL2)
The divisor latches can be accessed by setting the 7th bit of LCR to 1 . You should restore this bit to 0 after setting the divisor latches in order to restore access to the other registers that occupy the same addresses.
7 0
DL1
7 0
DL2
bit名 機能
DL1, DL2 The 2 bytes form one 16-bit register, which is internally accessed as a single number. You should therefore set all 2 bytes of the register to ensure normal operation. The register is set to the default value of 0 on reset, which disables all serial I/O operations in order to ensure explicit setup of the register in the software. The value set should be equal to (system clock speed) / (16 times desired baud rate). The internal counter starts to work when the LSB of DL is written, so when setting the divisor, write the MSB first and the LSB last.