VLSI design methodologies using hardware descrip- tion languages have been adopted to reduce VLSI design time. VLSIs are designed at the Register Transfer Level (RTL), and RTL circuits consist of a data path part and a controller part. The data path contains hardware element (e.g., registers, multiplexers, and operational modules) and signal lines. The controller, on the other hand, is represented by a finite state machine (FSM). The controller and the data path are interconnected by internal signals: control signals and status signals. A non-scan-based Design For Testabil- ity (DFT) method of the data path part is proposed in , whereas a non-scan-based DFT method for the controller part is proposed in . At-speed testing is possible and test patterns for a stuck-at fault model are completely generated using non-scan-based DFT methods. In , , both control signals from the controller and status signals from the data path were assumed to be directly controllable from primary inputs and observable at primary outputs. As mentioned above, if at-speed functional testing and/or delay testing are applied to VLSIs with a non-scan-based DFT, the test qual- ity can be further improved. As for the FSM, which is the controller part of an RTL circuit, the circuit specification is described explicitly. Thus, high test quality is expected by performing a logical fault testing and a timing fault testing under the constraints of the circuit specifications.
ステップ 2 で生成した組合せ回路要素 M に対する 観測経路が 2 入力演算モジュール M j を通る場合を考 える．観測経路が M jの非伝搬入力 x 上を通る場合，
M jの伝搬入力 x と出力ポート z 間にスルー機能が ない場合には，任意の値を伝搬できない．ここで， M jの y に定数を与えて x–z 間のスルー機能を実現でき る場合について考える．外部入力から M jの y へ定 数を印加 できれば， M jの x–z 間のス ルー機能を 新 たに付加する必要はないので，スルー機能実現のため
回路 C P ′ ともとの回路 C は分岐の位置が異なるだ
を C に印加したときの内部のゲート g i に割り当てら れる値と， v を C P ′ に印加したときの g i に対応する内 部のゲート g i ′ に割り当てられる値は同じである． v を 回路 C P ′ に印加したとき，ゲート g i ′ ∈ of f (f i ′ , P ′ ) が g i ′ = ncv(f i ′ ) と なって い た と す る と ， v を 回 路
Table 3 shows experiments reporting the time spent by dif- ferent stages of the constraint-driven untestability identification flow developed in this paper. As explained in the Introduc- tion, not all the modules (multiplexers F M and functional units F U ) in the RTL designs are affected by sequential untestability. Our method identified one module from gcd, three modules from mult8x8 and two modules from diffeq that had testability problems. Thus, only the above- mentioned six modules were considered in the hierarchical untestability proof by the constraint-driven logic-level ATPG. As it can be seen from the Table, the extraction of test path constraints required up to 1 min of run time. As discussed in Section 5 the constraint minimization step is very much de- pendent on the time-step bound. In the case of ADD2 the time- step bound k is 7 and the time for minimizing the constraints is accordingly more than 4,000 s. The test environment synthesis Table 4 Constraint-driven top-