Fig. 6 (a) Single-core bypass path by IEEE 1500 wrapper. (b) Multi-core bypass path by IEEE 1500 wrapper.
of making cores transparent as well as the cost of additional interconnect area simultaneously during optimization. (Additional Bypass Path) In the SoC design strategies, the behavioral models described using a hardware description language are not always available due to IP protection and so on. Even if it is available, it may happen that the total cost (including area and layout etc.) of making cores transparent by embedding multiplexers [23] is higher than that of bypass paths added outside of the cores since the embedded cores usually have IEEE 1500 wrappers and they can be used to configure the bypass paths. Figure 6 (a) shows an example of the bypass path using IEEE 1500 wrapper for the core used in Fig. 1 (a). In this example, a 4-bit bypass path from input wrapper boundary cells to output wrapper boundary cells is added outside of the core. Similarly, we can consider the multi-core bypass path (bypass path from a core input to another core output) by using IEEE 1500 wrappers as shown in Fig. 6 (b). In this paper, we use the term “single/multi- core bypass path” for the path implemented by IEEE 1500 wrappers while the term “transparent path” denotes the path implemented by embedded multiplexers. In transparency-
(1) p c 上にレジスタが存在する場合
p c 上にレジスタが存在する場合は TM を付加する. ここで, p c 上にある e 1 の直後のレジスタを r とす る. r の出力ポートを z ′ とし, r の直後の回路要素の 伝搬入力を x ′ とする.また, TM の二つの入力ポー トを x 及び y とし,出力ポートを z とする.このと き, TM を付加する場所について考える. TM を外部 入力に近い場所に付加すれば, TM を再利用できる可 能性が高くなり,面積オーバヘッドを縮小できると期
それほど 考慮が 必要とされず,上記の並列計算モデ ル
においても,通信コ ストの表現には 重点が おかれてい
† 奈良先端科学技術大学院大学情報科学研究科 ,生駒市
Graduate School of Information Science Nara Institute of Science and Technology, 8916–5 Takayama, Ikoma-shi, 630– 0101 Japan
NOT ゲートの出力にはファンアウトがないという回
図 1 ノンロバストテスト可能なパス遅延故障 Fig. 1 A non-robust testable path delay fault.
図 2 パスリーフ化変換(ステップ 1) Fig. 2 The first step of the path-leaf transformation.