Internal Target Registers Memory Map

3

DMA Registers

This section describes the DMA registers. The specified default state is defined as the state of the storage element when the PCI bus is reset. The pci_a function contains the following DMA registers:

■ Control and status

■ Address counter

■ Byte counter

■ Interrupt status

Control & Status Register (Offset = 00000 Hex)

The DMA control and status register (dma_csr) configures the pci_a DMA engine, directs the pci_a function’s DMA operation, and provides status of the current memory transfer. See Table 26.

Table 26. DMA Control & Status Register Format (Part 1 of 2)

Data Bit Mnemonic Read/Write Definition

0 int_ena Read/write PCI interrupt enable. The int_ena bit enables the intan output when either the err_pend or dma_tc bits are driven high from the dma_isr, or when the l_irqn signal is active.

1 flush Write Flush buffer. When high, flush marks all bytes in the internal EAB RAM queue as invalid and resets dma_tc and ad_loaded (bits 3 and 4 of the interrupt status register). The flush bit also resets itself;

therefore, it always reads as zero. The flush bit should never be set while dma_on is set, because a DMA transfer is in progress.

2 l_rst Read/write Local reset. This bit serves as a software reset to the local side add- on logic (see “Local Side Signals” on page 10). The l_reset output of the pci_a function is active as long as the l_rst bit is high. (The l_reset output is also active for PCI bus resets.)

3 write Read/write Memory read/write. The write bit determines the direction of the pci_a function’s DMA transfer. When write is high, the data flows from the local side to the PCI bus (PCI bus write); when write is low, the data flows from the PCI bus to the local device (PCI bus read).

4 dma_ena Read/write DMA enable. When high, dma_ena allows pci_a to respond to DMA requests from the local side (l_req) as long as the PCI bus activity is not stopped due to a pending interrupt, etc.

5 tci_dis Read/write Transfer complete interrupt disable. When high, tci_dis disables dma_tc (bit 3 of the DMA interrupt status register) from generating PCI bus interrupts.

Address Counter Register (Offset = 00004 Hex)

The DMA address counter register (dma_acr) is a 32-bit register consisting of a 30-bit counter (bits 31..2) and 2 bits (bits 1..0) tied to GND. The dma_acr contains the PCI bus address for the current memory transfer and is incremented after every data transfer on the PCI bus. PCI bus memory transfers initiated by the pci_a function must begin on DWORD boundaries. For monitoring progress, the dma_acr can be read via l_dma_acr_out[] ports. See Table 27.

Byte Counter Register (Offset = 00008 Hex)

The DMA byte counter register (dma_bcr) is a 17-bit register consisting of a 15-bit counter (bits 16..2) and 2 bits (bits 1..0) tied to GND. The dma_bcr holds the byte count for the current pci_a -initiated memory transfer and decrements (by 4 bytes) after every data transfer on the PCI bus. PCI bus memory transfers initiated by the pci_a function must be DWORD transfers. Reading the dma_bcr during a memory transfer can be achieved via the l_dma_bcr_out[] ports. See Table 28.

Data Bit Mnemonic Read/Write Definition

6 dma_on Read DMA on. When high, dma_on indicates that the pci_a function can request mastership of the PCI bus (reqn) if prompted by the local side (i.e., an active l_req). The dma_on bit is high when the address is loaded (ad_loaded), the DMA is enabled, and there are no pending errors. The DMA transfer sequence actually begins when the dma_on bit becomes set. Under normal conditions (i.e., DMA is enabled and no errors are pending) the dma_on bit becomes set when a write transaction to the DMA address counter register occurs.

The dma_on bit becomes set whether the write transaction occurs from the local side or via a target access.

31..7 Unused – –

Table 26. DMA Control & Status Register Format (Part 2 of 2)

Table 27. DMA Address Counter Register Format

Data Bit Name Read/Write Definition

1..0 dma_acr Read Bits are tied to GND

31..2 dma_acr Read/write 30-bit counter

3

The DMA interrupt status register (dma_isr) provides all interrupt source status signals to the interrupt handler. See Table 29.

Table 28. DMA Byte Counter Register Format

Data Bit Name Read/Write Definition

1..0 byte_cntr Read Bits are tied to GND.

16..2 byte_cntr Read/write 15-bit counter.

31..17 Unused – –

Table 29. DMA Interrupt Status Register Format

Data Bit Mnemonic Read/Write Definition

0 int_pend Read The pci_a function automatically asserts int_pend to indicate that a pci_a interrupt is pending. The three possible interrupt signals from the pci_a are err_pend, dma_tc, and int_irq.

1 err_pend Read When high, err_pend indicates that an error occurred during a pci_a-initiated PCI bus memory transfer, and that the interrupt handler must read the PCI configuration status register and clear the appropriate bits. Any one of the following three PCI status register bits can assert err_pend: mstr_abrt, tar_abrt, and det_par_err.

See “Control & Status Register (Offset = 00000 Hex)” on page 44.

2 int_irq Read When high, int_irq indicates that the local side is requesting an interrupt, i.e., the l_irqn input is asserted.

3 dma_tc Read When high, dma_tc indicates that the pci_a-initiated DMA transfer is complete. When the pci_a function sets the dma_tc bit, an interrupt will be generated on the intan output as long as interrupts are enabled by the int_ena bit (bit 0 of the dma_csr) and not disabled by the tci_dis bit (bit 5 of the dma_csr). The dma_tc bit is reset in one of three ways: a read transaction to the dma_isr; a write transaction to the dma_csr, which sets the flush bit (bit 1 of the dma_csr); or by writing to the dma_acr from the local side.

4 ad_loaded Read When high, ad_loaded indicates that the address has been loaded in the dma_acr. This bit is cleared in one of three ways: when the DMA operation is complete and the dma_tc bit is set; when the flush bit is set; or when the rstn input is asserted from the PCI bus. The ad_loaded bit triggers the beginning of a DMA operation because it sets the dma_on bit in the dma_acr register. It is automatically set by the pci_a when a write operation to the dma_acr is performed.

Therefore, the dma_acr should be written to last when a DMA