Power Factor Corrected LED Driver with Primary Side CC/CV NCL30488

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Power Factor Corrected LED Driver with Primary Side CC/CV

NCL30488

The NCL30488 is a power factor corrected flyback controller targeting isolated constant current LED drivers. The controller operates in a quasi−resonant mode to provide high efficiency. Thanks to a novel control method, the device is able to tightly regulate a constant LED current from the primary side. This removes the need for secondary side feedback circuitry, its biasing and for an optocoupler.

The device is highly integrated with a minimum number of external components. A robust suite of safety protection is built in to simplify the design.

Features

•

High Voltage Startup

•

Quasi−resonant Peak Current−mode Control Operation

•

Primary Side Feedback

•

CC / CV Accurate Control Vin up to 320 V rms

•

Tight LED Constant Current Regulation of ±2% Typical

•

Digital Power Factor Correction

•

Cycle by Cycle Peak Current Limit

•

Wide Operating V_CC Range

•

−40 to + 125°C

•

Robust Protection Features

♦ Brown−Out

♦ OVP on VCC

♦ Constant Voltage / LED Open Circuit Protection

♦ Winding Short Circuit Protection

♦ Secondary Diode Short Protection

♦ Output Short Circuit Protection

♦ Thermal Shutdown

♦ Line over Voltage Protection

•

This is a Pb−Free Device Typical Applications

•

Integral LED Bulbs

•

LED Power Driver Supplies

•

LED Light Engines

L30488XX ALYWX

G 1

8

SOIC−7 CASE 751U

See detailed ordering and shipping information on page 21 of this data sheet.

ORDERING INFORMATION MARKING

DIAGRAM

L30488 = Specific Device Code

XX = Version

A = Assembly Location

L = Wafer Lot

YW = Assembly Start Week G = Pb−Free Package

1

2

3

4

6

5 8

CS ZCD

GND DRV

HV

VCC COMP

PIN CONNECTIONS

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Figure 1. Typical Application Schematic for NCL30488 .

.

NCL30488

1 2 3

4 5

6 7

PIN FUNCTION DESCRIPTION NCL30488

Pin N5 Pin Name Function Pin Description

1 COMP OTA output for CV loop This pin receives a compensation network (capacitors and resistors) to stabilize the CV loop

2 ZCD Zero crossing Detection

V_aux sensing This pin connects to the auxiliary winding and is used to detect the core reset event.

This pin also senses the auxiliary winding voltage for accurate output voltage control.

3 CS Current sense This pin monitors the primary peak current.

4 GND − The controller ground

5 DRV Driver output The driver’s output to an external MOSFET

6 VCC Supplies the controller This pin is connected to an external auxiliary voltage.

7 NC creepage

8 HV High Voltage sensing This pin connects after the diode bridge to provide the startup current and internal high voltage sensing function.

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INTERNAL CIRCUIT ARCHITECTURE

Figure 2. Internal Circuit Architecture NCL30488

Leading Edge Blanking

Power factor and Constant−current control Zero crossing detection Logic

(ZCD blanking,Time−Out,…) Aux . Winding Short Circuit Prot.

Constant Voltage Control

Valley Selection Frequency foldback VCV

VREFX VVS

Max. Peak Current Limit COMP

CS

CS Short Protection Winding / Output diode

SCP

Maximum on−time

Driver and Clamp Line DRV

feed−forward

Q_drv VHVdiv

Aux_SCP Slow_OVP

Fast_OVP

Slow_OVP

Ipk_max

STOP

WOD_SCP

CS_short

HV Brown−out

Line OVP VHVdiv

BO_NOK

VHVdiv

STOP

VCC Management Fault

Management

Thermal Shutdown

VCC

VCC OVP UVLO

OFF

VCC_OVP Fast_OVP

Aux_SCP

STOP

CS_short

GND

Q_drv S

R Q Q

HV Startup

Standby ZCD

Standby

CS_reset VREFX

L_OVP L_OVP

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MAXIMUM RATINGS TABLE

Symbol Rating Value Unit

VCC(MAX)

I_CC(MAX) Maximum Power Supply voltage, VCC pin, continuous voltage

Maximum current for VCC pin −0.3 to 30

Internally limited V mA V_DRV(MAX)

I_DRV(MAX) Maximum driver pin voltage, DRV pin, continuous voltage

Maximum current for DRV pin −0.3, V_DRV (Note 1)

−300, +500 V mA V_HV(MAX)

IHV(MAX)

Maximum voltage on HV pin

Maximum current for HV pin (dc current self−limited if operated within the allowed range) −0.3, +700

±20 V

mA V_MAX

I_MAX Maximum voltage on low power pins (except pins DRV and VCC)

Current range for low power pins (except pins DRV and VCC) −0.3, 5.5 (Note 2)

−2, +5 V

mA

R_θJ−A Thermal Resistance Junction−to−Air 200 °C/W

T_J(MAX) Maximum Junction Temperature 150 °C

Operating Temperature Range −40 to +125 °C

Storage Temperature Range −60 to +150 °C

ESD Capability, HBM model except HV pin (Note 3) 4 kV

ESD Capability, HBM model HV pin 1.5 kV

ESD Capability, CDM model (Note 3) 1 kV

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

1. VDRV is the DRV clamp voltage VDRV(high) when VCC is higher than VDRV(high). VDRV is VCC otherwise.

2. This level is low enough to guarantee not to exceed the internal ESD diode and 5.5 V ZENER diode. More positive and negative voltages can be applied if the pin current stays within the −2 mA / 5 mA range.

3. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per Mil−Std−883, Method 3015.

Charged Device Model 1000 V per JEDEC Standard JESD22−C101D.

4. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.

ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T_J = 25°C, VCC = 12 V, V_ZCD = 0 V, V_CS = 0 V) For min/max values T_J = −40°C to +125°C, Max T_J = 150°C, V_CC = 12 V)

Parameter Test Condition Symbol Min Typ Max Unit

HIGH VOLTAGE SECTION

High voltage current source V_CC = V_CC(on) – 200 mV I_HV(start2) 3.9 5.1 6.2 mA

High voltage current source V_CC = 0 V I_HV(start1) − 300 − mA

V_CC level for I_HV(start1) to I_HV(start2) transition V_CC(TH) − 0.8 − V

Minimum startup voltage VCC = 0 V VHV(MIN) − 15 − V

HV source leakage current V_HV = 450 V I_HV(leak) − 4.5 10 mA

Maximum input voltage (rms) for correct operation of

the PFC loop VHV(OL) 320 − − V rms

SUPPLY SECTION Supply Voltage Startup Threshold

Minimum Operating Voltage Hysteresis V_CC(on) – V_CC(off) Internal logic reset

VCC increasing V_CC decreasing V_CC decreasing

VCC(on)

V_CC(off) V_CC(HYS) VCC(reset)

9.316 7.64

10.218

−5

10.720

−6 V

Over Voltage Protection

VCC OVP threshold V_CC(OVP) 25 26.5 28 V

V_CC(off) noise filter (Note 5)

V_CC(reset)noise filter (Note 5) t_VCC(off)

t_VCC(reset) −

− 5

20 −

− ms

Supply Current Device Disabled/Fault

Device Enabled/No output load on pin 5 Device Switching (F_sw = 65 kHz) Device switching (F_sw = 700 Hz)

V_CC > V_CC(off) Fsw = 65 kHz

C_DRV = 470 pF, F_sw = 65 kHz V_COMPv 0.9 V

I_CC1 ICC2

I_CC3 I_CC4

1.2–

−−

1.353.0 3.51.7

1.63.5 1.884.0

mA

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ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V, VCS = 0 V) For min/max values T_J = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V) (continued)

CURRENT SENSE

Maximum Internal current limit VILIM 1.33 1.40 1.47 V

Leading Edge Blanking Duration for V_ILIM t_LEB 283 345 407 ns

Propagation delay from current detection to gate

off−state tILIM − 100 150 ns

Maximum on−time (option 1) ton(MAX) 29 39 49 ms

Maximum on−time (option 2) t_on(MAX) 16 20 24 ms

Threshold for immediate fault protection activation

(140% of V_ILIM) V_CS(stop) 1.9 2.0 2.1 V

Leading Edge Blanking Duration for V_CS(stop) t_BCS − 170 − ns

Current source for CS to GND short detection I_CS(short) 400 500 600 mA

Current sense threshold for CS to GND short

detection V_CS rising V_CS(low) 20 60 90 mV

GATE DRIVE Drive Resistance DRV Sink

DRV Source R_SNK

R_SRC −

− 13

30 −

− W

Drive current capability DRV Sink (Note GBD)

DRV Source (Note GBD) ISNK

I_SRC −

− 500

300 −

− mA

Rise Time (10% to 90%) C_DRV= 470 pF t_r – 30 − ns

Fall Time (90 %to 10%) C_DRV= 470 pF t_f – 20 − ns

DRV Low Voltage VCC = VCC(off)+0.2 V

C_DRV= 470 pF, R_DRV= 33 kW VDRV(low) 8 – − V

DRV High Voltage VCC = VCC(MAX)

C_DRV= 470 pF, R_DRV= 33 kW VDRV(high) 10 12 14 V ZERO VOLTAGE DETECTION CIRCUIT

Upper ZCD threshold voltage V_ZCD rising VZCD(rising) − 90 150 mV

Lower ZCD threshold voltage VZCD falling VZCD(falling) 35 55 − mV

Threshold to force V_REFX maximum during startup V_ZCD falling V_ZCD(start) − 0.7 − V

ZCD hysteresis VZCD(HYS) 15 − − mV

Propagation Delay from valley detection to DRV high

(no t_LEB4) V_ZCD decreasing t_ZCD(DEM) − − 150 ns

Additional delay from valley lockout output to DRV

latch set (programmable option) V_ZCD decreasing T_LEB4 125 250 375 ns

Equivalent time constant for ZCD input (GBD) t_PAR − 20 − ns

Blanking delay after on−time (option 1) VREFX > 0.35 V tZCD(blank1) 1.1 1.5 1.9 ms Blanking delay after on−time (option 2) V_REFX > 0.35 V tZCD(blank1) 0.75 1.0 1.25 ms Blanking Delay at light load (option 1) V_REFX < 0.25 V tZCD(blank2) 0.6 0.8 1.0 ms Blanking Delay at light load (option 2) V_REFX < 0.25 V tZCD(blank2) 0.45 0.6 0.75 ms

Timeout after last DEMAG transition t_TIMO 5 6.5 8 ms

Pulling−down resistor VZCD = VZCD(falling) RZCD(pd) − 200 − kW

CONSTANT CURRENT CONTROL

Reference Voltage T_j = 25°C − 85°C V_REF/3 327.9 334.2 341.2 mV

Reference Voltage T_j = −40°C to 125°C V_REF/3 324 334.2 346 mV

Current sense lower threshold for detection of the

leakage inductance reset time V_CS falling V_CS(low) 20 50 100 mV

Blanking time for leakage inductance reset detection t_CS(low) − 120 − ns

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POWER FACTOR CORRECTION

Clamping value for VREF(PFC) TJ = 0°C to 125°C VREF(PFC)CLP 2.06 2.2 2.34 V

Line range detector for PFC loop V_HV increases V_HL(PFC) − 240 − Vdc

Line range detector for PFC loop V_HV decreases V_LL(PFC) − 230 − Vdc

CONSTANT VOLTAGE SECTION

Internal voltage reference for constant voltage

regulation V_REF(CV) 3.41 3.52 3.63 V

CV Error amplifier Gain G_EA 40 50 60 mS

Error amplifier current capability VREFX = VREF (no dimming) IEA − ±60 − mA

COMP pin lower clamp voltage V_CV(clampL) − 0.6 − V

COMP pin higher clamp voltage TJ = 0°C to 125°C VCV(clampH) 4.05 4.12 4.25 V

COMP pin higher clamp voltage T_J = −40°C to 125°C V_CV(clampH) 4.01 4.12 4.25 V

Internal divider V_COMP to V_REFX K_COMP − 4 −

Internal ZCD voltage below which the CV OTA is

boosted V_REF(CV)* 85% V_boost(CV) 2.796 2.975 3.154 V

Threshold for releasing the CV boost V_REF(CV)* 90% Vboost(CV)RST 2.96 3.15 3.34 V

Error amplifier current capability during boost phase I_EAboost − ±140 − mA

ZCD OVP 1^st level (slow OVP) option 1 VREF(CV) * 115% VOVP1 3.783 4.025 4.267 V ZCD voltage at which slow OVP is exit (option 1) V_REF(CV)* 105% V_OVP1rst − 3.675 − V

Switching period during slow OVP Tsw(OVP1) − 1.5 − ms

ZCD fast OVP option 1 V_ref(CV)* 125% + 150 mV V_OVP2 4.253 4.525 4.797 V

Number of switching cycles before fast OVP

confirmation T_{OVP2_CNT} − 4 −

Duration for disabling DRV pulses during ZCD fast

OVP T_recovery − 4 − s

COMP pin internal pullup resistor (SSR option) R_pullup − 15 − kW

LINE FEED FORWARD

V_HV to I_CS(offset) conversion ratio K_LFF 0.189 0.21 0.231 mA/V

Offset current maximum value VHV > (450 V or 500 V) Ioffset(MAX) 76 95 114 mA

Line feed−forward current DRV high, V_HV= 200 V I_FF 35 40 45 mA

VALLEY LOCKOUT SECTION

Threshold for line range detection V_HV increasing (1^st to 2^nd valley transition for V_REFX > 80% V_REF) (prog. option: 1^st to 3^rd valley transition)

V_HV increases V_HL 228 240 252 V

Threshold for line range detection V_HV decreasing (2^nd to 1^st valley transition for V_REFX > 80% V_REF) (prog. option: 3^rd to 1^st valley transition)

V_HV decreases V_LL 218 230 242 V

Blanking time for line range detection t_HL(blank) 15 25 35 ms

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VALLEY LOCKOUT SECTION Valley thresholds

1^st to 2^nd valley transition at LL and 2^nd to 3^rd valley HL, V_REF decr. (prog. option: 3^rd to 4^th valley HL) 2^nd to 1^st valley transition at LL and 3^rd to 2^nd valley HL, V_REF incr. (prog. option: 4^th to 3^rd valley HL) 2^nd to 3^rd valley transition at LL and 3^rd to 4^th valley HL, VREF decr. (prog. option: 4^th to 5^th valley HL) 3^rd to 2^nd valley transition at LL and 4^th to 3^rd valley HL, V_REF incr. (prog. option: 5^th to 4^th valley HL) 3^rd to 4^th valley transition at LL and 4^th to 5^th valley HL, V_REF decr. (prog. option: 5^th to 6^th valley HL) 4^th to 3^th valley transition at LL and 5^th to 4^th valley HL, VREF incr. (prog. option: 6^th to 5^th valley HL) 4^th to 5^th valley transition at LL and 5^th to 6^th valley HL, V_REF decr. (prog. option: 6^th to 7^th valley HL) 5^th to 4^th valley transition at LL and 6^th to 5^th valley HL, VREF incr. (prog. option: 7^th to 6^th valley HL)

V_REF decreases VREF increases V_REF decreases V_REF increases VREF decreases V_REF increases V_REF decreases V_REF increases

V_{VLY1−2/2−3} VVLY2−1/3−2

V_{VLY2−3/3−4} V_{VLY3−2/4−3} VVLY3−4/4−5

V_{VLY4−3/5−4} V_{VLY4−5/5−6} V_{VLY5−4/6−5}

−

0.80 0.90 0.65 0.75 0.50 0.60 0.35 0.45

−

− V

V_REF value at which the FF mode is activated V_REF decreases V_FFstart − 0.25 − V

V_REF value at which the FF mode is removed V_REF increases V_FFstop − 0.35 − V

FREQUENCY FOLDBACK

Added dead time V_REFX = 0.25 V t_FF1LL 0.8 1.0 1.2 ms

Added dead time V_REFX = 0.08 V t_FFchg − 40 − ms

Dead−time clamp ( option 1) V_REFX < 3 mV t_FFend1 − 675 − ms

Dead−time clamp ( option 2) V_REFX < 11.2 mV t_FFend2 − 250 − ms

Minimum added dead−time in standby VREFX = 0 tDT(min)SBY − 650 − ms

Maximum added dead−time in standby (option 2) V_REFX = 0, V_COMP < 0.7 V tDT(max)SBY2 − 1.8 − ms FAULT PROTECTION

Thermal Shutdown (Note 5) Device switching (F_SW

around 65 kHz) T_SHDN 130 150 170 °C

Thermal Shutdown Hysteresis T_SHDN(HYS) − 20 – °C

Threshold voltage for output short circuit or aux.

winding short circuit detection V_ZCD(short) 0.6 0.65 0.7 V

Short circuit detection Timer V_ZCD < V_ZCD(short) t_OVLD 70 90 110 ms

Auto−recovery Timer t_recovery 3 4 5 s

Line OVP threshold V_HV increasing V_HV(OVP) 457 469 485 Vdc

HV pin voltage at which Line OVP is reset VHV decreasing VHV(OVP)RST 430 443 465 Vdc

Blanking time for line OVP reset TLOVP(blank) 15 25 35 ms

BROWN−OUT AND LINE SENSING

Brown−Out ON level (IC start pulsing) V_HV increasing V_HVBO(on) 101.5 108 114.5 Vdc Brown−Out ON level (IC start pulsing) option 2 V_HV increasing V_HVBO(on)2 129.7 138 146.3 Vdc

Brown−Out OFF level (IC stops pulsing) VHV decreasing VHVBO(off) 92 98 104 Vdc

Brown−Out OFF level (IC stops pulsing) option 2 V_HV decreasing V_HVBO(off)2 121 129 137 Vdc HV pin voltage above which the sampling of ZCD is

enabled low line VHV decreasing, low line VsampENLL − 55 − V

HV pin voltage above which the sampling of ZCD is

enabled highline VHV decreasing, highline VsampENHL − 105 − V

ZCD sampling enable comparator hysteresis VHV increasing VsampHYS − 5 − V

BO comparators delay t_BO(delay) − 30 − ms

Brown−Out blanking time t_BO(blank) 15 25 35 ms

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

5. Guaranteed by design.

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TYPICAL CHARACTERISTICS

Figure 3. I_HV(start2) vs. Temperature Figure 4. I_HV(start1) vs. Temperature

Figure 5. V_HV(OL) vs. Temperature Figure 6. V_CC(on) vs. Temperature

Figure 7. V_CC(off) vs. Temperature Figure 8. V_CC(OVP) vs. Temperature

4,5 4,6 4,7 4,8 4,9 5 5,1 5,2 5,3 5,4

−50 −25 0 25 50 75 100 125

IHV(start2) (mA)

TEMPERATURE (°C)

349 351 353 355 357 359 361

−50 −25 0 25 50 75 100 125

VHV(OL) (V rms)

284 289 294 299 304 309

−50 −25 0 25 50 75 100 125

IHV(start1) (mA)

TEMPERATURE (°C)

18,14 18,19 18,24 18,29 18,34

−50 −25 0 25 50 75 100 125

VCC(on) (V)

10,11 10,13 10,15 10,17 10,19 10,21 10,23 10,25

−50 −25 0 25 50 75 100 125

VCC(off) (V)

26,66 26,71 26,76 26,81 26,86 26,91 26,96

−50 −25 0 25 50 75 100 125

VCC(OVP) (V)

TEMPERATURE (°C) TEMPERATURE (°C)

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TYPICAL CHARACTERISTICS (continued)

Figure 9. I_CC1 vs. Temperature Figure 10. I_CC4 vs. Temperature

Figure 11. V_ILIM vs. Temperature Figure 12. V_CS(low)F vs. Temperature

Figure 13. V_CS(stop) vs. Temperature Figure 14. t_on(MAX)2 vs. Temperature

1,29 1,31 1,33 1,35 1,37 1,39 1,41

−50 −25 0 25 50 75 100 125

ICC1 (mA)

1,62 1,63 1,64 1,65 1,66 1,67 1,68 1,69 1,7

−50 −25 0 25 50 75 100 125

ICC4 (mA)

−50 −25 0 25 50 75 100 125

VILIM (V)

50 50,5 51 51,5 52 52,5 53 53,5 54

−50 −25 0 25 50 75 100 125

VCS(low)F (mV)

1,94 1,96 1,98 2 2,02 2,04 2,06

−50 −25 0 25 50 75 100 125

VCS(stop) (V)

19,84 19,89 19,94 19,99 20,04 20,09 20,14 20,19 20,24

−50 −25 0 25 50 75 100 125

ton(MAX)2 (ms)

1.386 1.388 1.390 1.392 1.394 1.396 1.398 1.400 1.402 1.404

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Figure 15. t_LEB vs. Temperature Figure 16. t_BCS vs. Temperature

Figure 17. t_ILIM vs. Temperature Figure 18. R_SNK vs. Temperature

Figure 19. R_SRC vs. Temperature Figure 20. t_r vs. Temperature

334 339 344 349 354 359

−50 −25 0 25 50 75 100 125 172

173 174 175 176 177 178 179 180

−50 −25 0 25 50 75 100 125

tBCS (ns)

50 60 70 80 90 100 110 120

−50 −25 0 25 50 75 100 125

tILIM (ns)

3,5 4,5 5,5 6,5 7,5 8,5 9,5 10,5

−50 −25 0 25 50 75 100 125

RSNK (W)

5,5 7,5 9,5 11,5 13,5 15,5

−50 −25 0 25 50 75 100 125

RSRC (W)

20 22 24 26 28 30 32 34

−50 −25 0 25 50 75 100 125

tr (ns)

tLEB (ns)

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Figure 21. t_f vs. Temperature Figure 22. VZCD(rising) vs. Temperature

Figure 23. VZCD(falling) vs. Temperature Figure 24. V_ZCD(short) vs. Temperature

Figure 25. t_ZCD(dem) vs. Temperature Figure 26. tZCD(blank1)OPN1 vs. Temperature

12,5 13,5 14,5 15,5 16,5 17,5 18,5 19,5 20,5 21,5

−50 −25 0 25 50 75 100 125

tF (ns)

79 79,5 80 80,5 81 81,5 82 82,5 83

−50 −25 0 25 50 75 100 125

VZCD(rising) (mV)

49,5 50,5 51,5 52,5 53,5 54,5

−50 −25 0 25 50 75 100 125

VZCD(falling) (mV)

0,658 0,66 0,662 0,664 0,666 0,668 0,67 0,672

−50 −25 0 25 50 75 100 125

VZCD(short) (V)

76 81 86 91 96 101 106 111 116

−50 −25 0 25 50 75 100 125

tZCD(DEM) (ns)

1,555 1,565 1,575 1,585 1,595 1,605

−50 −25 0 25 50 75 100 125

tZCD(blank1)OPN1 (ms)

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Figure 27. tZCD(blank1)OPN2 vs. Temperature Figure 28. tZCD(blank2)OPN1 vs. Temperature

Figure 29. tZCD(blank2)OPN2 vs. Temperature Figure 30. t_TIMO vs. Temperature

Figure 31. V_REF/3 vs. Temperature Figure 32. V_REF(CV) vs. Temperature

1,042 1,047 1,052 1,057 1,062 1,067 1,072

−50 −25 0 25 50 75 100 125

0,836 0,841 0,846 0,851 0,856 0,861

−50 −25 0 25 50 75 100 125

0,564 0,569 0,574 0,579 0,584

−50 −25 0 25 50 75 100 125

6,72 6,77 6,82 6,87 6,92

−50 −25 0 25 50 75 100 125

tTIMO (ms)

331,8 332,3 332,8 333,3 333,8 334,3 334,8 335,3 335,8 336,3 336,8

−50 −25 0 25 50 75 100 125

VREF/3 (mV)

TEMPERATURE (°C)

3,475 3,485 3,495 3,505 3,515 3,525 3,535 3,545

−50 −25 0 25 50 75 100 125

VREF(CV) (V)

TEMPERATURE (°C)

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Figure 33. V_CV(clampH) vs. Temperature Figure 34. V_OVP1 vs. Temperature

Figure 35. V_OVP2 vs. Temperature Figure 36. K_LFF vs. Temperature

Figure 37. Ioffset(MAX) vs. Temperature Figure 38. I_FF vs. Temperature

4,08 4,09 4,1 4,11 4,12 4,13 4,14 4,15

−50 −25 0 25 50 75 100 125

VCV(clampH) (V)

3,995 4,005 4,015 4,025 4,035 4,045 4,055 4,065 4,075

−50 −25 0 25 50 75 100 125

VOVP1 (V)

4,49 4,5 4,51 4,52 4,53 4,54

−50 −25 0 25 50 75 100 125

VOVP2 (V)

0,2005 0,2015 0,2025 0,2035 0,2045 0,2055 0,2065 0,2075 0,2085 0,2095

−50 −25 0 25 50 75 100 125

KLFF (mA/V)

96 97 98 99 100 101 102 103 104

−50 −25 0 25 50 75 100 125

Ioffset(MAX) (mA)

40,1 40,3 40,5 40,7 40,9 41,1 41,3 41,5 41,7

−50 −25 0 25 50 75 100 125

IFF (mA)

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Figure 39. t_FF1LL vs. Temperature Figure 40. VREF(PFC)CLP vs. Temperature

Figure 41. VHVBO(on)ONP1 vs. Temperature Figure 42. V_HVBO(off) vs. Temperature

Figure 43. V_HV(OVP) vs. Temperature Figure 44. V_HV(OVP)RST vs. Temperature

1,0305 1,0315 1,0325 1,0335 1,0345 1,0355 1,0365 1,0375 1,0385 1,0395

−50 −25 0 25 50 75 100 125

tFF1LL (ms)

2,168 2,173 2,178 2,183 2,188 2,193 2,198 2,203 2,208

−50 −25 0 25 50 75 100 125

VREF(PFC)CLP (V)

106,9 107,1 107,3 107,5 107,7 107,9 108,1 108,3 108,5 108,7 108,9

−50 −25 0 25 50 75 100 125

VHVBO(on)OPN1 (V)

TEMPERATURE (°C)

97,8 98 98,2 98,4 98,6 98,8 99 99,2 99,4 99,6

−50 −25 0 25 50 75 100 125

VHVBO(off)OPN1 (V)

TEMPERATURE (°C)

464 465 466 467 468 469 470 471 472

−50 −25 0 25 50 75 100 125

VHV(OVP) (V dc)

TEMPERATURE (°C)

439 440 441 442 443 444 445 446

−50 −25 0 25 50 75 100 125

VHV(OVP)RST (V dc)

TEMPERATURE (°C)

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Application Information

The NCL30488 implements a current−mode architecture operating in quasi−resonant mode. Thanks to proprietary circuitry, the controller is able to accurately regulate the secondary side current and voltage of the fly−back converter without using any opto−coupler or measuring directly the secondary side current or voltage. The controller provides near unity power factor correction

•

Quasi−Resonance Current−Mode Operation:

implementing quasi−resonance operation in peak current−mode control, the NCL30488 optimizes the efficiency by switching in the valley of the MOSFET drain−source voltage. Thanks to an internal algorithm control, the controller locks−out in a selected valley and remains locked until the input voltage or the output current set point significantly changes.

•

Primary Side Constant Current Control: thanks to a proprietary circuit, the controller is able to take into account the effect of the leakage inductance of the transformer and allows an accurate control of the secondary side current regardless of the input voltage and output load variation.

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Primary Side Constant Voltage Regulation: By monitoring the auxiliary winding voltage, it is possible to regulate accurately the output voltage. The output voltage regulation is typically within ±2%.

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Load Transient Compensation: Since PFC has low loop bandwidth, abrupt changes in the load may cause excessive over or under−shoot. The slow Over Voltage Protection contains the output voltage when it tends to become excessive. In addition, the NCL30488 speeds up the constant voltage regulation loop when the output voltage goes below 85% of its regulation level.

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Power Factor Correction: A proprietary concept allows achieving high power factor correction and low THD while keeping accurate constant current and constant voltage control.

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Line Feed−forward: allows compensating the variation of the output current caused by the propagation delay.

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^VCC Over Voltage Protection: if the VCC pin voltage exceeds an internal limit, the controller shuts down and waits 4 seconds before restarting pulsing.

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Fast Over Voltage Protection: If the voltage of ZCD pin exceeds 130% of its regulation level, the controller shuts down and waits 4 s before trying to restart.

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Brown−Out: the controller includes a brown−out circuit which safely stops the controller in case the input voltage is too low. The device will automatically restart if the line recovers.

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Cycle−by−cycle peak current limit: when the current sense voltage exceeds the internal threshold VILIM, the MOSFET is turned off for the rest of the switching cycle.

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Winding Short−Circuit Protection: an additional comparator senses the CS signal and stops the controller

if VCS reaches 1.5 x VILIM (after a reduced LEB of tBCS).

This additional comparator is enabled only during the main LEB duration t_LEB, for noise immunity reason.

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Output Under Voltage Protection: If a too low voltage is applied on ZCD pin for 90 ms time interval, the controllers assume that the output or the ZCD pin is shorted to ground and shutdown. After waiting 4 seconds, the IC restarts switching.

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Thermal Shutdown: an internal circuitry disables the gate drive when the junction temperature exceeds 150°C (typically). The circuit resumes operation once the temperature drops below approximately 140°C.

POWER FACTOR AND CONSTANT CURRENT CONTROL

The NCL30488 embeds an analog/digital block to control the power factor and regulate the output current by monitoring the ZCD, CS and HV pin voltages (signals VZCD, VHV_DIV, VCS). This circuit generates the current setpoint signal and compares it to the current sense signal to turn the MOSFET off. The HV pin provides the sinusoidal reference necessary for shaping the input current. The obtained current reference is further modulated so that when averaged over a half line period, it is equal to the output current reference (V_REFX). The modulation and averaging process is made internally by a digital circuit. If the HV pin properly conveys the sinusoidal shape, power factor will be close to 1. Also, the Total Harmonic Distortion (THD) will be low especially if the output voltage ripple is small.

I_OUT+ V_REF

2NspRsense (eq. 1)

Where:

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Nsp is the secondary to primary transformer turns ratio:

Nsp = NS / NP

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^Rsense is the current sense resistor

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^VREFX is the output current reference: V_REFX = V_REF if no dimming

The output current reference (V_REFX) is V_REF unless the controller operates in constant voltage mode.

PRIMARY SIDE CONSTANT VOLTAGE CONTROL The auxiliary winding voltage is sampled internally through the ZCD pin.

A precise internal voltage reference V_REF(CV) sets the voltage target for the CV loop.

The sampled voltage is applied to the negative input of the constant voltage (CV) operational transconductance amplifier (OTA) and compared to VREFCV.

A type 2 compensator is needed at the CV OTA output to stabilize the loop. The COMP pin voltage modify the the output current internal reference in order to regulate the output voltage.

When VCOMP ≥ 4 V, VREFX = VREF. When VCOMP < 0.9 V, V_REFX = 0 V.