NCL30085 Power Factor Corrected Quasi-Resonant Primary Side Current-Mode Controller for LED Lighting with Line Step Dimming and Thermal Foldback

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Power Factor Corrected Quasi-Resonant Primary Side Current-Mode

Controller for LED Lighting with Line Step Dimming and Thermal Foldback

The NCL30085 is a power factor corrected flyback controller targeting isolated and non−isolated constant current LED drivers. The controller operates in a quasi−resonant mode to provide optimal efficiency. Thanks to a novel control method, the device is able to tightly regulate a constant LED current from the primary side. This removes the need for secondary side feedback circuitry, biasing and an optocoupler.

The device is highly integrated with a minimum number of external components. A robust suite of safety protection is built in to simplify the design. This device is specifically intended for very compact, space efficient designs and supports 3 levels of log step dimming which allows light output reduction by toggling the main AC switch on and off to signal the controller to reduce the LED current point down to 5% of full load.

Features

•

Quasi−resonant Peak Current−mode Control Operation

•

Constant Current Control with Primary Side Feedback

•

Tight LED Constant Current Regulation of ±2% Typical

•

Power Factor Correction

•

3 Step Dimming (70/25/5%)

•

Line Feedforward for Enhanced Regulation Accuracy

•

Low Start−up Current (10 mA typ.)

•

^{Wide V}cc Range

•

300 mA / 500 mA Totem Pole Driver with 12 V Gate Clamp

•

Robust Protection Features

♦ OVP on V_CC

♦ Programmable Over Voltage / LED Open Circuit Protection

♦ Cycle−by−cycle Peak Current Limit

♦ Winding Short Circuit Protection

♦ Secondary Diode Short Protection

♦ Output Short Circuit Protection

♦ Current Sense Short Protection

♦ User Programmable NTC Based Thermal Foldback

♦ Thermal Shutdown

♦ Vcc Undervoltage Lockout

♦ Brown−out Protection

•

Pb−Free, Halide−Free MSL1 Product Typical Applications

•

Integral LED Bulbs and Tubes

•

LED Light Engines

•

LED Drivers/Power Supplies

www.onsemi.com

SOIC−8 NB CASE 751

PIN CONNECTIONS MARKING DIAGRAM

(Top View)

L30085x = Specific Device Code x = A, B

A = Assembly Location L = Wafer Lot

Y = Year

W = Work Week G = Pb-Free Package

See detailed ordering and shipping information in the package dimensions section on page 26 of this data sheet.

ORDERING INFORMATION V_CC DRV GND 1

CS VS

COMP ZCD

SD

1 8

L30085x ALYW

G 1 8

(2)

1 2 3

4 5

8

6 7

. . Aux

.

NCL30085

sense

R

Figure 1. Typical Application Schematic for NCL30085

Table 1. PIN FUNCTION DESCRIPTION

Pin No Pin Name Function Pin Description

1 ZCD Zero Crossing Detection Connected to the auxiliary winding, this pin detects the core reset event.

2 VS Input Voltage Sensing This pin observes the input voltage rail and protects the LED driver in case of too low mains conditions (brown−out).

This pin also observes the input voltage rail for:

− Power Factor Correction

− Valley lockout

− Step dimming

3 COMP Filtering Capacitor This pin receives a filtering capacitor for power factor correction. Typical values ranges from 1 − 4.70 mF

4 SD Thermal Foldback and

Shutdown

Connecting an NTC to this pin allows the user to program thermal current foldback threshold and slope. A Zener diode can also be used to pull−up the pin and stop the controller for adjustable OVP protection.

5 CS Current Sense This pin monitors the primary peak current.

6 GND − Controller ground pin.

7 DRV Driver Output The driver’s output to an external MOSFET

8 V_CC IC Supply Pin This pin is the positive supply of the IC. The circuit starts to operate when V_CC exceeds 18 V and turns off when V_CC goes below 8.8 V (typical values). After start−up, the operating range is 9.4 V up to 26 V (V_{CC (OVP )} minimum level).

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Internal Circuit Architecture

SD Thermal

Foldback

Over Temp. Protection Over Voltage Protection

ZCD Zero Crossing Detection Logic

(ZCD Blanking, Time−Out, ...) Valley Selection

CS Power Factor and

Constant−Current Control Leading

Edge Blanking

Winding and Output diode Short Circuit Protection Max. Peak Current Limit

Ipkmax

WOD_SCP DRV

VCC Management

VCC

DRV VCC Over Voltage

Protection

VCC Internal

Thermal Shutdown (Auto−recovery or Latched)

Fault Management

Clamp Circuit

VS Brown−Out

BO_NOK S

R Q Q

CS_reset

STOP

UVLO OFF

Latch

STOP WOD_SCP BO_NOK

GND STOP

Aux. Winding Short Circuit Prot. Aux_SCP Aux_SCP

VCC_max

FF_mode

V Line

feed−forward

VS V_VS

Ipkmax

V_TF V_TF

V_REF V_DD

V_REF V_VS

Enable

CS Short Protection

CS_ok

V_REF Frequency Foldback

FF_mode

STEP_DIM Maximum on time

VREFX VREFX

UVLO t_on,max

on,max t

Dimming control V_VS V_REFX

COMP

Figure 2. Internal Circuit Architecture

(Auto−recovery or Latched)

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V_CC(MAX) I_CC(MAX)

Maximum Power Supply voltage, V_CC pin, continuous voltage Maximum current for V_CC pin

−0.3 to 30 Internally limited

V mA V_DRV(MAX)

I_DRV(MAX)

Maximum driver pin voltage, DRV pin, continuous voltage Maximum current for DRV pin

−0.3, V_DRV (Note 1)

−300, +500

V mA V_MAX

I_MAX

Maximum voltage on low power pins (except DRV and V_CC pins) Current range for low power pins (except DRV and V_CC pins)

−0.3, 5.5 (Notes 2 and 5)

−2, +5

V mA

R_θ_J−A Thermal Resistance Junction−to−Air 180 °C/W

T_J(MAX) Maximum Junction Temperature 150 °C

Operating Temperature Range −40 to +125 °C

Storage Temperature Range −60 to +150 °C

ESD Capability, HBM model (Note 3) 3.5 kV

ESD Capability, MM model (Note 3) 250 V

ESD Capability, CDM model (Note 3) 2 kV

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

1. V_DRV is the DRV clamp voltage V_DRV(high) when V_CC is higher than V_DRV(high). V_DRV is V_CC otherwise.

2. This level is low enough to guarantee not to exceed the internal ESD diode and 5.5−V Zener diode. More positive and negative voltages can be applied if the pin current stays within the −2−mA / 5−mA range.

3. This device contains ESD protection and exceeds the following tests: Human Body Model 3500 V per JEDEC Standard JESD22−A114E, Machine Model Method 250 V per JEDEC Standard JESD22−A115B, Charged Device Model 2000 V per JEDEC Standard JESD22−C101E.

4. This device contains latch−up protection and has been tested per JEDEC Standard JESD78D, Class I and exceeds ±100 mA 5. Recommended maximum V_S voltage for optimal operation is 4 V. −0.3 V to +4.0 V is hence, the V_S pin recommended range.

Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values T_J = 25°C, V_CC = 12 V, V_ZCD = 0 V, V_CS = 0 V, V_SD = 1.5 V) For min/max values T_J = −40°C to +125°C, V_CC = 12 V)

Description Test Condition Symbol Min Typ Max Unit

STARTUP AND SUPPLY CIRCUITS Supply Voltage

Startup Threshold

Minimum Operating Voltage Hysteresis V_CC(on) – V_CC(off) Internal logic reset

V_CC rising V_CC rising V_CC falling

V_CC(on) V_CC(off) V_CC(HYS) V_CC(reset)

16.0 8.2 8 4

18.0 8.8

− 5

20.0 9.4

− 6

V

V_CC Over Voltage Protection Threshold V_CC(OVP) 25.5 26.8 28.5 V

V_CC(off) noise filter V_CC(reset)noise filter

t_VCC(off) t_VCC(reset)

−

− 5 20

−

ms

Startup current I_CC(start) − 13 30 mA

Startup current in fault mode I_CC(sFault) 58 75 mA

Supply Current Device Disabled/Fault

Device Enabled/No output load on pin 7 Device Switching (F_SW = 65 kHz)

V_CC > V_CC(off) F_sw = 65 kHz C_DRV = 470 pF, F_sw = 65 kHz

I_CC1 I_CC2 I_CC3

0.8 –

−

1.0 2.5 3.0

1.2 4.0 4.5

mA

CURRENT SENSE

Maximum Internal current limit V_ILIM 0.95 1.00 1.05 V

Leading Edge Blanking Duration for V_ILIM t_LEB 240 300 360 ns

Line feed−forward current DRV high, V_VS= 2 V I_FF 35 40 45 mA

6. Guaranteed by Design

7. A NTC is generally placed between the SD and GND pins. Parameters R_TF(start), R_TF(stop), R_OTP(off)andR_OTP(on) give the resistance the NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after an OTP situation.

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CURRENT SENSE

Propagation delay from current detection to gate off−state

t_ILIM − 100 150 ns

Maximum on−time t_on(MAX) 26 36 46 ms

Threshold for immediate fault protection activation V_CS(stop) 1.35 1.50 1.65 V

Leading Edge Blanking Duration for V_CS(stop) t_BCS − 150 − ns

Current source for CS to GND short detection I_CS(short) 400 500 600 mA

Current sense threshold for CS to GND short detection

V_CS rising V_CS(low) 30 65 100 mV

GATE DRIVE Drive Resistance

DRV Sink DRV Source

R_SNK R_SRC

−

− 13 30

−

W

Drive current capability DRV Sink (Note 6) DRV Source (Note 6)

I_SNK I_SRC

−

500 300

−

mA

Rise Time (10% to 90%) C_DRV= 470 pF t_r – 40 − ns

Fall Time (90% to 10%) C_DRV= 470 pF t_f – 30 − ns

DRV Low Voltage V_CC = V_CC(off)+0.2 V

C_DRV= 470 pF, R_DRV=33 kW

V_DRV(low) 8 – − V

DRV High Voltage V_CC = V_CC(MAX)

C_DRV= 470 pF, R_DRV=33 kW

V_DRV(high) 10 12 14 V

ZERO VOLTAGE DETECTION CIRCUIT

Upper ZCD threshold voltage V_ZCD rising VZCD(rising) − 90 150 mV

Lower ZCD threshold voltage V_ZCD falling VZCD(falling) 35 55 − mV

ZCD hysteresis V_ZCD(HYS) 15 − − mV

Propagation Delay from valley detection to DRV high V_ZCD falling T_DEM − 100 300 ns Blanking delay after on−time V_REFX > 30% V_REF TZCD(blank1) 1.12 1.50 1.88 ms Blanking Delay at light load V_REFX < 25% V_REF TZCD(blank2) 0.56 0.75 0.94 ms

Timeout after last DEMAG transition T_TIMO 5.0 6.5 8.0 ms

Pulling−down resistor V_ZCD= VZCD(falling) R_ZCD(PD) − 200 − kW

CONSTANT CURRENT AND POWER FACTOR CONTROL

Reference Voltage at T_J = 25°C V_REF 245 250 255 mV

Reference Voltage T_J = 25°C to 100°C V_REF 242.5 250.0 257.5 mV

Reference Voltage T_J = −40°C to 125°C V_REF 240 250 260 mV

Current sense lower threshold V_CS falling V_CS(low) 20 50 100 mV

V_control to current setpoint division ratio V_ratio − 4 − −

Error amplifier gain V_REFX=V_REF (no dimming)

V_REFX=25%* V_REF

G_EA 40 50

200

60 mS

8. At startup, when V reaches V , the controller blanks OTP for more than 250 ms to avoid detecting an OTP fault by allowing the

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Description Test Condition Symbol Min Typ Max Unit CONSTANT CURRENT AND POWER FACTOR CONTROL

Error amplifier current capability V_REFX=V_REF (no dimming) V_REFX=25%* V_REF

I_EA ±60

±240

mA

COMP Pin Start−up Current Source No dimming, COMP pin grounded

I_{EA_STUP} 140 mA

LINE FEED FORWARD

V_VS to I_CS(offset) conversion ratio K_LFF 18 20 22 mS

Line feed−forward current on CS pin DRV high, V_VS= 2 V I_FF 35 40 45 mA

Offset current maximum value V_VS> 5 V Ioffset(MAX) 80 100 120 mA

VALLEY LOCKOUT SECTION

Threshold for high− line range (HL) detection V_VS rising V_HL 2.28 2.40 2.52 V Threshold for low−line range (LL) detection V_VS falling V_LL 2.18 2.30 2.42 V

Blanking time for line range detection t_HL(blank) 15 25 35 ms

Valley Lockout

First step valley in High−Line.

Second step valley in High−Line.

Third step valley in High−Line.

First step valley in Low−Line.

Second step valley in Low−Line.

Third step valley in Low−Line.

V_HL100%

V_HL70%

V_HL25%

V_LL100%

V_LL70%

V_LL25%

2 3 6 1 2 5 FREQUENCY FOLDBACK

Additional dead time V_REFX = 25%*V_REF t_FF1LL 1.4 2.0 2.6 ms

Additional dead time V_REFX = 5%*V_REF t_FF2HL − 40 − ms

FAULT PROTECTION

Thermal Shutdown (Note 6) F_SW = 65 kHz T_SHDN 130 150 170 _C

Thermal Shutdown Hysteresis T_SHDN(HYS) − 50 – _C

Threshold voltage for output short circuit or aux.

winding short circuit detection

V_ZCD(short) 0.8 1.0 1.2 V

Short circuit detection Timer V_ZCD < V_ZCD(short) t_OVLD 70 90 110 ms

Auto−recovery timer duration t_recovery 3 4 5 s

SD pin Clamp series resistor R_SD(clamp) 1.6 kW

Clamped voltage SD pin open V_SD(clamp) 1.13 1.35 1.57 V

SD pin detection level for OVP V_SD rising V_OVP 2.35 2.50 2.65 V

Delay before OVP or OTP confirmation (OVP and OTP)

T_SD(delay) 22.5 30.0 37.5 ms Reference current for direct connection of an NTC

(Note 8)

I_OTP(REF) 80 85 90 mA

Fault detection level for OTP (Note 7) V_SD falling V_OTP(off) 0.47 0.50 0.53 V SD pin level for operation recovery after an OTP

detection

V_SD rising V_OTP(on) 0.66 0.70 0.74 V

8. At startup, when V_CC reaches V_CC(on), the controller blanks OTP for more than 250 ms to avoid detecting an OTP fault by allowing the SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin.

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FAULT PROTECTION

OTP blanking time when circuit starts operating (Note 8)

t_OTP(start) 250 370 ms

SD pin voltage at which thermal fold−back starts (V_REF is decreased)

V_TF(start) 0.94 1.00 1.06 V

SD pin voltage at which thermal fold−back stops (V_REF is clamped to V_REF50)

V_TF(stop) 0.64 0.69 0.74 V

V_TF(start) over I_OTP(REF) ratio (Note 7) T_J = +25°C to +125°C R_TF(start) 10.8 11.7 12.6 kW V_TF(stop) over I_OTP(REF) ratio (Note 7) T_J = +25°C to +125°C R_TF(stop) 7.4 8.1 8.8 kW V_OTP(off) over I_OTP(REF) ratio (Note 7) T_J = +25°C to +125°C R_OTP(off) 5.4 5.9 6.4 kW V_OTP(on) over I_OTP(REF) ratio (Note 7) T_J = +25°C to +125°C R_OTP(on) 7.5 8.1 8.7 kW V_REFX @ V_SD = 600 mV (percent of V_REF) SD pin falling, no OTP

detection

V_REF(50) 40 50 60 %

BROWN−OUT

Brown−Out ON level (IC start pulsing) V_S rising V_BO(on) 0.95 1.00 1.05 V

Brown−Out OFF level (IC shuts down) V_S falling V_BO(off) 0.85 0.90 0.95 V

BO comparators delay t_BO(delay) 30 ms

Brown−Out blanking time t_BO(blank) 15 25 35 ms

V_S pin Pulling−down Current V_S= V_BO(on) I_BO(bias) 50 250 450 nA

Step Dimming Reset Time V_S < V_BO(off) t_step−reset 2.4 3.2 4.0 s

8. At startup, when V_CC reaches V_CC(on), the controller blanks OTP for more than 250 ms to avoid detecting an OTP fault by allowing the SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin.

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Figure 3. V_CC Start−up Threshold vs.

Temperature

Figure 4. V_CC Minimum Operating Voltage vs.

Temperature

T_J, JUNCTION TEMPERATURE (°C) T_J, JUNCTION TEMPERATURE (°C) 125

100 75 50 25 0

−25

−50 16.0 16.5 17.0 17.5 18.0 19.0 19.5

125 100 75 50 25 0

−25

−50 8.2 8.3 8.5 8.7 8.9 9.0 9.2

Figure 5. Hysteresis (V_CC(on) − V_CC(off)) vs.

Temperature

Figure 6. V_CC(reset) vs. Temperature T_J, JUNCTION TEMPERATURE (°C) T_J, JUNCTION TEMPERATURE (°C)

125 100 75 50 25 0

−25

−50 7.5 8.0 8.5 9.0 9.5 10.5 11.0 11.5

125 100 75 50 25 0

−25

−50 4.0 4.2 4.6 4.8 5.0 5.4 5.8 6.0

VCC(on) (V) VCC(off) (V)

VCC(hys) (V) VCC(reset) (V)

150 18.5

150 8.4

8.6 8.8 9.1 9.3

150 10.0

150 4.4

5.2 5.6

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TYPICAL CHARACTERISTICS

Figure 7. V_CC Over Voltage Protection Threshold vs. Temperature

Figure 8. Start−up Current vs. Temperature T_J, JUNCTION TEMPERATURE (°C) T_J, JUNCTION TEMPERATURE (°C)

125 100 75 50 25 0

−25

−50 25.6 26.0 26.2 26.6 27.0 27.4 27.6 28.0

125 100 75 50 25 0

−25

−50 0 5 10 15 20 30 35 40

Figure 9. Start−up Current in Fault Mode vs.

Temperature

Figure 10. I_CC1 vs. Temperature T_J, JUNCTION TEMPERATURE (°C) T_J, JUNCTION TEMPERATURE (°C)

125 100 75 50 25 0

−25

−50 0 25 50 75 100 125 150

125 100 75 50 25 0

−25

−50 0.4 0.6 0.8 1.0 1.2 1.6 1.8 2.0

Figure 11. I_CC2 vs. Temperature Figure 12. I_CC3 vs. Temperature T_J, JUNCTION TEMPERATURE (°C) T_J, JUNCTION TEMPERATURE (°C)

125 100 75 50 25 0

−25

−50 1.2 1.6 2.0 2.4 2.6 3.0 3.4 3.8

125 100 75 50 25 0

−25

−50 1.0 1.5 2.0 2.5 3.0 4.0 4.5 5.0

VCC(ovp) (V) ICC(start) (mA)

ICC(sfault) (mA) ICC1 (mA)

ICC2 (mA) ICC3 (mA)

150 25.8

26.4 26.8 27.2 27.8

150 25

150 150

1.4

150 1.4

1.8 2.2 2.8 3.2 3.6

150 3.5

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Figure 13. Maximum Internal Current Limit vs.

Temperature

Figure 14. Leading Edge Blanking vs.

Temperature

100 75 50 25 0

−25

−50 0.95 0.97 0.98 1.00 1.03

125 100 75 50 25 0

−25

−50 200 220 240 260 280 320 340

Figure 15. Current Limit Propagation Delay vs.

Temperature

Figure 16. Maximum On−time vs. Temperature T_J, JUNCTION TEMPERATURE (°C) T_J, JUNCTION TEMPERATURE (°C)

125 100 75 50 25 0

−25

−50 0 10 50 70 100 120 150

125 100 75 50 25 0

−25

−50 30 32 34 38 40 44 48 50

Figure 17. V_CS(stop) vs. Temperature Figure 18. Leading Edge Blanking Duration for V_CS(stop) vs. Temperature

100 75 50 25 0

−25

−50 1.38 1.42 1.46 1.48 1.50 1.54 1.60

125 100 75 50 25 0

−25

−50 100 110 130 140 170 210 220

VILIM (V) TLEB (ns)

TILIM (ns) TON(max) (ms)

VCS(stop) (V) TBCS (ns)

150 0.96

0.99 1.01 1.02 1.04

150 300

150 150

42

150 1.40

1.44 1.52 1.58

150 180

360 380

20 30 40 60 80 90 110 130 140

36 46

1.56

120 150 190

160 200

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Figure 19. I_CS(short) vs. Temperature Figure 20. V_CS(low), V_CS Rising vs.

Temperature

100 75 50 25 0

−25

−50 400 420 440 480 540 560 600

125 100 75 50 25 0

−25

−50 20 30 40 50 60 80 90 100

Figure 21. Sink Gate Drive Resistance vs.

Temperature

Figure 22. Source Gate Drive Resistance vs.

Temperature

100 75 50 25 0

−25

−50 0 2 6 10 12 16 20

125 100 75 50 25 0

−25

−50 10 14 16 20 24 32 36 40

Figure 23. Gate Drive Rise Time vs.

Temperature

Figure 24. Gate Drive Fall Time (C_DRV = 470 pF) vs. Temperature T_J, JUNCTION TEMPERATURE (°C) T_J, JUNCTION TEMPERATURE (°C)

125 100 75 50 25 0

−25

−50 0 15 25 35 40 50

125 100 75 50 25 0

−25

−50 0 5 10 20 25 40 45 50

ICS(short) (mA) VCS(low) (mV)

RSNK (W) RSRC (W)

tr (ns) tF (ns)

150 460

500 520 580

150 70

150 150

28

150 5

10 20 30 45

150 30

4 8 14 18

12 18 22 26 30 34 38

15 35

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Figure 25. DRV Low Voltage vs. Temperature Figure 26. DRV High Voltage vs. Temperature T_J, JUNCTION TEMPERATURE (°C) T_J, JUNCTION TEMPERATURE (°C)

125 100 75 50 25 0

−25

−50 8.2 8.4 8.6 8.8 9.4

125 100 75 50 25 0

−25

−50 10.0 10.5 11.0 12.0 12.5 13.5 14.5

Figure 27. Upper ZCD Threshold Voltage vs.

Temperature

Figure 28. Lower ZCD Threshold vs.

Temperature

100 75 50 25 0

−25

−50 30 50 70 90 100 130 150

125 100 75 50 25 0

−25

−50 30 35 40 50 55 70 75 80

Figure 29. ZCD Hysteresis vs. Temperature Figure 30. ZCD Blanking Delay vs.

Temperature

100 75 50 25 0

−25

−50 0 5 15 25 35 40 50

125 100 75 50 25 0

−25

−50 1.0 1.1 1.2 1.4 1.5 1.7 1.9 2.0

VDRV(low) (V) VDRV(high) (V)

VZCD(rising) (mV) VZCD(falling) (mV)

VZCD(HYS) (mV) tZCD(blank1) (ms)

150 9.0

9.2 9.6

150 13.0

150 150

60

150 10

20 30 45

150 1.6

11.5 14.0

40 60 80 110 120 140

45 65

1.3 1.8

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Figure 31. ZCD Time−out vs. Temperature Figure 32. Reference Voltage vs. Temperature T_J, JUNCTION TEMPERATURE (°C) T_J, JUNCTION TEMPERATURE (°C)

125 100 75 50 25 0

−25

−50 5.8 6.2 6.6 7.0 7.2 7.4 7.8

125 100 75 50 25 0

−25

−50 244 245 247 248 250 253 254 256

Figure 33. Current Sense Lower Threshold (V_CS Falling) vs. Temperature

Figure 34. Error Amplifier Trans−conductance Gain vs. Temperature

100 75 50 25 0

−25

−50 10 20 40 60 80 90 110

125 100 75 50 25 0

−25

−50 42 44 46 48 50 56 58 60

Figure 35. Feedforward V_VS to I_CS(offset) Conversion Ratio vs. Temperature

Figure 36. Line Feedforward Current on CS Pin (@ V_VS = 2 V) vs. Temperature T_J, JUNCTION TEMPERATURE (°C) T_J, JUNCTION TEMPERATURE (°C)

125 100 75 50 25 0

−25

−50 18.0 18.5 19.0 20.0 21.5 22.0

125 100 75 50 25 0

−25

−50 36 37 38 39 40 42 43 44

TTIMO (ms) VREF (mV)

VCS(low) (mV) GEA (mS)

KLFF (mS) IFF (mA)

150 6.0

6.4 6.8 7.6

150 251

150 150

54

150 19.5

20.5 21.0

150 41

246 249 252 255

30 50 70 100

52

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Figure 37. Ioffset(MAX) vs. Temperature Figure 38. Threshold for High−line Range Detection vs. Temperature T_J, JUNCTION TEMPERATURE (°C) T_J, JUNCTION TEMPERATURE (°C)

125 100 75 50 25 0

−25

−50 80 85 90 95 110

125 100 75 50 25 0

−25

−50 2.25 2.30 2.35 2.40 2.50

Figure 39. Threshold for Low−line Range Detection vs. Temperature

Figure 40. Blanking Time for Low−line Range Detection vs. Temperature

100 75 50 25 0

−25

−50 2.20 2.25 2.35 2.40 2.50 2.55 2.60

125 100 75 50 25 0

−25

−50 20 22 24 28 30 34 38 40

Figure 41. Threshold Voltage for Output Short Circuit Detection vs. Temperature

Figure 42. Short Circuit Detection Timer vs.

Temperature

100 75 50 25 0

−25

−50 0.80 0.85 1.00 1.15 1.20

125 100 75 50 25 0

−25

−50 75 80 85 90 95 105 110 115

Ioffset(MAX) (mA) VHL (V)

VLL (V) THL(blank) (ms)

VZCD(short) (V) tOVLD (ms)

150 100

105 115

150 2.45

150 150

32

150 0.90

0.95 1.05 1.10

150 100

2.30 2.45

26 36

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Figure 43. Auto−recovery Timer Duration vs.

Temperature

Figure 44. SD Pin Clamp Series Resistor vs.

Temperature

100 75 50 25 0

−25

−50 3.00 3.25 3.50 3.75 4.50 5.00

125 100 75 50 25 0

−25

−50 1.00 1.10 1.30 1.40 1.60 1.90 2.00 2.20

Figure 45. SD Pin Clamp Voltage vs.

Temperature

Figure 46. SD Pin OVP Threshold Voltage vs.

Temperature

100 75 50 25 0

−25

−50 1.10 1.15 1.30 1.35 1.45 1.50 1.60

125 100 75 50 25 0

−25

−50 2.40 2.42 2.44 2.46 2.50 2.54 2.56 2.58

Figure 47. T_SD(delay) vs. Temperature Figure 48. I_OTP(REF) vs. Temperature T_J, JUNCTION TEMPERATURE (°C) T_J, JUNCTION TEMPERATURE (°C)

125 100 75 50 25 0

−25

−50 22 24 30 38

125 100 75 50 25 0

−25

−50 79 80 82 83 85 88 89 91

Trecovery (s) RSD(clamp) (kW)

VSD(clamp) (V) VOVP (V)

TSD(delay) (ms) IOTP(REF) (mA)

150 4.00

4.25 4.75

150 1.70

150 150

2.52

150 26

28 32 34 36

150 86

1.20 1.50 1.80 2.10

1.20 1.25 1.40 1.55

2.48

81 84 87 90