令和 3 年度修士論文

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令和 3 年度修士論文

電荷モード折り返し AD 変換回路の研究

Charge-Domain

Folding Analog-to-Digital Converter

指導教員小林春夫教授桑名杏奈助教

群馬大学大学院理工学府理工学専攻電子情報・数理教育プログラム

学籍番号 T191D603

李雄炎

LI XIONGYAN

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This thesis deals with a charge-domain CMOS folding analog-to-digital converter. A folding analog-to-digital converter is used as a high-speed AD conversion circuit with bipolar or CMOS technology; it can achieve high sampling speed equivalent to the flash type with the circuit amount and power consumption at a fraction of the flash type. In the conventional method, the folding analog-to-digital converter is realized in the current mode, but in this paper, its realization with the charge mode (switched capacitor method) is examined. With this method, a high-speed, low-power CMOS A-D converter can be realized with a relatively simple circuit configuration.

The folding ADC requires only one comparator for each bit with analog preprocessing circuits; hence, it is required only a small hardware and its power consumption is small for 5-bit or 6-bit resolution. Also, our designed charge mode folding ADC using discrete-time signal processing using TSMC 0.18μm CMOS is shown. It may suffer from nonlinearity due to device mismatches, but it will be noise- shaped inside the modulator and its effects will be alleviated. Its circuit design and simulation results are shown.

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1.Introduction

1.1 Research background

With the rapid development of modern science and technology, especially digital systems have been widely used in various disciplines and daily life, microcomputers are a typical mathematical system. But the digital system can only process the digital input signal, and its output signal is also a digital signal. Many physical quantities in industrial detection control and life are continuously changing analog quantities, such as temperature, pressure, flow, speed and so on. These analog quantities can be changed into corresponding voltage, current or frequency through sensors or transducers, as an isoelectric analog quantity. In order to realize the detection, operation and control of these electrical analog quantities by the digital system, a process of mutual conversion between analog and digital quantities is required. That is, it is often necessary to convert analog quantities into digital quantities, referred to as AD conversion. The circuit that completes this conversion is called analog to digital converter (Analog to Digital Converter), referred to as ADC. Conversion of digital quantities into analog quantities, is referred to as DA conversion. The circuit that completes this conversion is called a digital to analog converter (Digital to Analog Converter), referred to as DAC.

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1.2 Research Objective

In modern times, with the widespread use of computers and the digital communication and information technology development, ADC and DAC have become more and more important [1-7].It is almost a hundred years since the first computer came out. In this century, rapid development of digital electronics technology has played an irreplaceable role in all walks of life, and people cannot leave it in their daily lives.

We accept these analog signals and convert them into digital signals.Here in the ADC area, the folding analog-to-digital converter is the object of our research, and the objective is development of CMOS fast and small circuit ADC architecture. Our approach is using folding ADC architecture plus CMOS nonlinear switched capacitor circuit to obtain digital signals.

1.3 Introduction to ADC

An analog-to-digital converter, or ADC for short, usually refers to an electronic component that converts an analog signal into a digital signal. The usual analog-to- digital converter converts an input voltage signal into an output digital signal, as shown in Fig.1.Since the digital signal itself has no practical meanings, it only represents a

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convertible signal size. The output digital quantity represents the magnitude of the input signal relative to the reference signal.

Fig.1 Analog-to-digital converter

One of the most important performance indices of the analog-to-digital converter is the accuracy of the conversion, which is usually expressed by the number of bits of the output digital signal. The more digits of the digital signal that the converter can accurately output, the stronger the ability of the converter to distinguish the input signal and the better the performance of the converter.

AD conversion generally involves four processes of sampling, holding, quantization and encoding. In the actual circuit, some processes are combined, such as sampling and holding, quantization and coding are realized at the same time in the conversion process.

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Any natural signal is an analog signal. In daily life, people's voice is an analog signal, body temperature is an analog signal, and the pressure of a finger on the screen is also an analog signal. We accept these analog signals and convert them into digital signals.

The world we exist in is an analog world, basically all analog measurements, such as light, sound, acceleration, speed, altitude, humidity and so on. These signals are converted into voltage signals and then digitized for DSP processing.All real-world things need to be converted by various sensors through ADC before they can be processed by digital systems, as shown in Fig. 2. [13] Without ADC, your CPU and all digital systems are wasted. The best example is the smartphone in your hand. The CPU inside can interact with the outside world through various sensors (such as cameras), and the ADC is an indispensable bridge between sensors and the CPU.

Fig.2. ADC application fields

1.3.1 Sampling Rate

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a parameter to indicate the rate at which the new digital signal is sampled from the analog signal. This rate is called the sampling rate or sampling frequency of the converter. See Fig.3. [13]

It can collect continuously changing and bandwidth-limited signals (measure and store a signal value every other time), and then restore the converted discrete signal to the original signal through interpolation. The accuracy of this process is limited by the quantization error. However, only when the sampling rate is higher than twice the signal frequency can it be faithfully restored to the original signal.

This law is reflected in the sampling theorem.

Since the actual analog-to-digital converter cannot perform complete real-time conversion, some additional methods must be used to keep it constant during a conversion of the input signal. A sample-and-hold circuit is commonly used. In most cases, a capacitor can be used to store the input analog voltage, and a switch or gate circuit can be used to close and disconnect the capacitor and the input signal.

Many analog-to-digital conversion integrated circuits already include such a sample-and-hold subsystem internally.

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Fig.3. Sampling frequency

1.3.2 ADC Resolution

The resolution of the A/D converter is expressed by the number of bits in the output binary (or decimal) number. It shows the resolution ability of the A/D converter to the input signal. Theoretically speaking, an A/D converter with n-bit output can distinguish two different levels of input analog voltage, and the minimum value of the input voltage that can be distinguished is 1 2⁄ ^𝑛 of the full-scale input. When the maximum input voltage is constant, the more the number of output bits, the higher the resolution. See Fig.4. [13]

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Fig.4. Example for ADCs resolution

1.3.3 Effective Number of Bits

Effective number of bits (ENOB) is a measure of the dynamic range of analog-digital converters and their associated circuits. The resolution of the ADC is specified by the number of bits used to represent the analog value, which in principle gives a 2N signal level for an N-bit signal. However, all actual ADC circuits contain noise and distortion.

ENOB is one point to the resolution of an ideal ADC circuit having the same resolution as that of the circuit is taken into account.

ENOB (shown in Fig.5[13]) is also used as a quality measure for other blocks such as sample / hold amplifiers. In this way, analog blocks can be easily included in the signal chain calculation. This is because the total ENOB of the blockchain is usually smaller than the ENOB of the lowest block. ENOB is expressed by such a famous formula:

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𝑺𝑵𝑹[𝒅𝑩] = 𝟔. 𝟎𝟐𝑵 + 𝟏. 𝟕𝟔 [𝒅𝑩]

𝑬𝑵𝑶𝑩 = (𝑺𝑵𝑹 − 𝟏. 𝟕𝟔) 𝟔. 𝟎𝟐⁄ [bits]

Fig.5. Example for Effective Number of Bits.

1.3.4 ADC SNDR

Signal-to-noise-distortion ratio (SNDR) is usually expressed in dB. SNDR is a standard metric for analog-to-digital conversion circuits and digital-to-analog conversion circuits. The signal-to-noise ratio (SNR) is the ratio of signal energy to quantization noise energy, but this is only an ideal situation for ADC, that is, only quantization noise is considered, but the actual situation is thermal noise, quantization noise and harmonic distortion are interfering with the signal, so the actual measurement

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calculated after FFT analysis. This quantity is used to measure how much the signal is affected by noise during ADC conversion. See Fig.6. [13]

Fig.6. Example for ADC SNDR.

1.3.5 Differential Non-linearity (DNL)

Differential Nonlinearity (DNL) error is defined as the difference between the actual quantization step and the ideal value corresponding to 1LSB. See Fig.8. Differential nonlinearity error is the distance between adjacent codes measured on each quantization step. It is usually the analog increase offset value introduced by the non-ideal factors of the circuit components, in percentage or LSB. The conversion error is usually given in the form of the maximum value of the output error. It represents the difference between the actual output digital quantity of the A/D converter and the theoretical output digital

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quantity. It is often expressed as a multiple of the least significant bit (LSB). For example, if the relative error is less than or equal to ±LSB/2, it means that the error between the actual output digital quantity and the theoretical output digital quantity is less than the lowest half word. Notice that 1LSB=Full Scale/2^𝑛. See Fig.7. [13]

Fig.7. Example for LSB

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Fig.8. Example for DNL

1.3.6 Integral Non-linearity (INL)

The integral nonlinear error (INL) of the analog-to-digital converter is used to measure the maximum difference between the actual characteristic curve and the ideal characteristic curve, which is usually expressed as a percentage or LSB.

If the actual step deviates by 1 LSB from the ideal step, that is, when DNL = -1 LSB, two major problems occur. One is the phenomenon of missing code, in which the digital output signal corresponding to the analog input signal is not output. The other is that when the analog input signal is increased, the monotonicity that the digital output signal simply increases is lost. When these phenomena occur, the accuracy is greatly deteriorated. See Fig.9.

Fig.9. Example for INL

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1.3.7 Gain error

The input and output of the ADC module have a linear relationship. But in fact, the ADC module has gain error and offset error. The gain error is the deviation between the slope of the actual curve and the slope of the ideal curve. The offset error (or offset error) is the actual output value and the ideal value at 0 V input. Deviation between output values (0 V). See Fig.10.

Fig.10. Example for Gain error.

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1.3.8 Offset error

The difference between the ideal output of the device and the actual output is defined as the offset error, which is present in all digital codes. In practice, the offset error will cause a fixed offset between the transfer function or analog input voltage and the corresponding numerical output code. The usual method of calculating the offset error is to measure the voltage of the first digital code transition or "zero" transition and compare it with the theoretical zero point voltage. The gain error is the difference between the estimated transfer function and the actual slope. The gain error is usually calculated at the last or transfer code conversion point of the analog-to-digital converter.

1.3.9 ADC Figure of Merit (FOM)

FOM is a function used to express the performance of the ADC. The objective is to establish measures to compare performance of various ADCs. FOM is not a fixed function. We can use FOM to combine several performance metrics to get one single number. In 1993, the International Conference on Solid State Electronics put forward a figure of merit formula that includes these three indicators to measure the performance of the converter:

FOM= 𝐩𝐨𝐰𝐞𝐫 (𝐬𝐚𝐦𝐩𝐥𝐢𝐧𝐠 𝐫𝐚𝐭𝐞 × 𝟐⁄ ^{𝑬𝑵𝑶𝑩})

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1.3.10 ADC Architectures

There are several common types of an electronic ADC.Flash ADC, folding ADC, sequential comparison ADC and pipeline ADC, oversampling ADC (ΔΣ ADC).

The flash ADC performs the AD conversion of n-bit output, by preparing 2^𝑛 -1 comparators and a digital thermometer-to-binary encoder. For example, if AD conversion is performed from 0V to 15V at 1V intervals to obtain a 4-bit output, by preparing 15 comparators from 1V to 15V to perform input and comparison, and encoding those outputs in binary if necessary. The principle is simple, and the result is obtained only by the operation of the comparator, so it is very fast. However, as the number of bits increases, the number of comparators increases rapidly. An example is shown in Fig. 11. [12]

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Fig.11 Example for Flash ADC

Sequential comparison ADC is based on the principle to test and compare from the high position to the low position one by one. The conversion process of the successive approximation method is as follows: Clear the bits of the successive approximation register to zero during initialization; at the beginning of the conversion, first set the highest position of the successive approximation register to 1, send it to the D/A converter, and send the analog quantity generated after the D/A conversion. The comparator, called Vo, is compared with the analog quantity Vi sent to the comparator to be converted. If Vo<Vi, the bit 1 is reserved, otherwise it is cleared. Then set the next highest bit of the successive approximation register to 1, send the new digital value in the register to the D/A converter, and compare the output Vo with Vi. If Vo<Vi, the bit

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1 is reserved, otherwise it is cleared. Repeat this process until the lowest bit of the register is approached. After the conversion, the digital quantity in the successive approximation register is sent to the buffer register to obtain the output of the digital quantity.

The Σ-Δ ADC digitizes the analog signal with a very low sampling resolution (1 bit) and a high sampling rate and increases the effective resolution by using methods such as oversampling, noise shaping, and digital filtering, and then samples the ADC output Decimation processing to reduce the effective sampling rate. The circuit structure of the Σ-Δ ADC is composed of a very simple analog circuit and a very complicated digital signal processing circuit. The example is shown in Fig.12.

Fig.12 Example for Σ-Δ ADC

The pipeline type is one of the circuit methods that realizes an AD converter that converts an analog signal into a digital signal. It is installed in communication equipment and video equipment. In the pipeline type AD converter, multiple AD converters with low resolution such as 1 bit or 1.5 bit are prepared, and an analog signal is converted into a digital signal using a pipeline circuit in which these are connected

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Fig.13 Example for pipeline ADC

Typical circuit methods for realizing AD converters include pipeline type, sequential comparison (SAR: Successive Approximation Register), delta-sigma (delta-sigma) type, and flash type. Every method has both strong and weak aspects. Among them, the pipeline type is a circuit method with relatively few areas of weakness. In other words, a high sampling rate of tens of meters to hundreds of meters per second can be obtained, and at the same time, high resolution of 12 bits, 14 bits, and 16 bits can be achieved.

Other than the pipeline type, those with high resolution tend to have a low sampling rate, and those with a high sampling rate tend to have a low resolution.

ADC configuration circuit is made of sample hold circuits and comparators.

Sampling is the conversion of an analog quantity that changes continuously with time into a time-discrete analog quantity. Fig.14 shows the structure of the sampling circuit,

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where the transmission gate is controlled by the sampling signal S(t). During the pulse width τ of S(t), the transmission gate is turned on, and the output signal 𝑣_𝑜 (t) is the input signal v1, and During (Ts-τ), the transmission gate is closed and the output signal 𝑣_𝑜(t)=0. The wave of each signal in the circuit is shown in Fig15.

Fig.14. Example for sample hold circuit

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Fig.15 the structure of the sampling circuit

The comparator (Fig.16) can be used as a 1-bit analog-to-digital converter (ADC).

The operational amplifier can be used as a comparator in principle without negative feedback, but because the open-loop gain of the operational amplifier is very high, it can only process signals with a very small input differential voltage. Moreover, in general, the delay time of the operational amplifier is long, which cannot meet the actual demand. The comparator can be adjusted to provide a very small time delay, but its frequency response characteristics will be limited. To avoid output oscillation, many comparators also have internal hysteresis circuits. The threshold of the comparator is fixed, some have only one threshold, and some have two thresholds. And the Fig.17 shows the example for ADC configuration.

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Fig.16. Example for Comparators

Fig.17. Example for ADC configuration

2. Conventional High-Speed ADCs

2.1 Flash ADC

First, the 3-bit flash ADC is introduced. Fig.18 shows a typical 3-bit flash ADC

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The bottom resistance is grounded. It has an array of seven comparators to receive voltage signals and convert them into digital signal. Following the comparator array, a digital encoder circuit is employed. Finally, the binary digital output is obtained.

Fig.18. 3-bit Flash ADC configuration

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Fig.19 Truth table of digital encoder

Fig.19 shows the truth table of the digital encoder. When the analog input Vin is the 3.56 V, it isworked by comparator array and finally binary digital output.In case that Vin is 4.5 V, all of the seven comparators will work. But only two comparators with the reference voltage of 4 V or 5V are working effectively, and others are redundant.

The flash ADC has 3 obvious characteristics.

(i) It is the fastest ADC.

(ii) It has the large hardware.

For example, an N-bit Flash ADC has 2^𝑛-1 comparator. In case of 3-bit the flash ADC has 7 comparators.

(iii) Hence it consumes a lot of power.

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2.3 Binary Code and Gray Code

Frank Gray at Bell Lab invented Gray code in 1947. Gray code is robust code compared to binary code.It is a coding method that minimizes errors. Although the natural binary code can be directly converted into an analog signal by a digital-to- analog converter, in some cases, for example, when converting from decimal 3 to 4, every bit of the binary code has to change, which can make the digital circuit produce a lot of large spike current pulses. The Gray code does not have this shortcoming.

When it switches between adjacent bits, only one bit changes. It greatly reduces the logic confusion when going from one state to the next. Since there is only one bit difference between the two adjacent code groups of this kind of code, in the conversion of the angular displacement of the direction to the digital value, when the angular displacement of the direction changes slightly which may cause the digital value to occur. When changing, the Gray code only changes one bit, which is more reliable than other codes where two or more bits are changed at the same time, and the possibility of errors can be reduced.

Fig.20 shows some Gray code icon. Gray code is often used in ADC, and in this paper, we use it. Fig.21 shows binary code versus Gray code.

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Fig.20 Gray code

Fig.21.Binary Code versus Gray Code

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2.2 Current-Domain Folding ADC

There are many types of current folding converters, and then features of the folding ADC are described. The folding ADC is the fastest ADC. It utilizes analog encoding circuit so that the folding ADC can remove “redundancy of flash ADC”. [1-7]

The folding ADC has small hardware, and it uses the comparators. For example, an N-bit folding ADC has N comparators. 3-bit (N=3) case has 3 comparators. Fig.22 shows Gray code digital output with respect to the analog input Vin.

Fig.22. Gray code digital output with respect to analog input Vin

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2.4 Current-Mode Analog Encoder

The folding A-D converter connects the drain outputs of multiple differential pairs alternately on the plus side and the minus side, to perform analog encoding in the current mode. A conventional current-mode type folding circuit with a Gray code output is shown in Fig. 23. Only one comparator is required per bit, and since a digital encoding circuit is not required, the circuit scale and power consumption can be significantly reduced. Moreover, since there is no feedback, high-speed sampling can be realized.

(a) Current-Mode Analog Encoder for G3

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(c) Current-Mode Analog Encoder for G1

Fig.23. Current-Mode folding circuits for G3(a) G2(b) and G1(c) generation Only one comparator is used for each G3, G2, G1, and the amplifier circuit is used as analog encoder. Fig. 24 shows the SPICE simulation results in the circuit of Fig. 23.

(a) SPICE simulation result of the circuit in G3

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(b) SPICE simulation result of the circuit in G2

(c) SPICE simulation result of the circuit in G1 Fig.24. SPICE simulation result of the circuit in fig.6

2.5 Features of Analog Encoder

The advantage of analog encoder is that effective for hardware reduction. Because

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high current drivability. But it not suitable for CMOS circuit(operation is slow),due to its low current drivability.

3. Proposed Charge-Domain Folding ADC

3.1 Consideration of CMOS Folding ADC

We describe here our charge mode folding ADC design with TSMC 0.18μm CMOS process and 3V supply voltage. Its circuit and SPICE simulation results are shown.

We have designed a 6-bit folding ADC. The resolution of 6-bit can be easily realized with simple hardware.

Its digital output is provided in Gray code format, as shown in Fig. 25, and the Gray code can be converted to the binary code using exclusive OR (EXOR) gates; the 2-input EXOR gate can be realized with 2 PMOSFETs and 2 NMOSFETs [8].

Fig. 25. Gray code digital output with respect to analog input Vin

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3.2 Preamplifier Circuit

The preamplifier circuit and its SPICE simulation results are shown in Fig.26.

Preamplifier saturation characteristics is used and nonlinear switched capacitor folding circuit can be designed.

(a) Circuit configuration.

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(c) Power consumption of preamplifier.

Fig.26. Pre-amplifier circuit.

We have performed some SPICE simulations to investigate NMOS and PMOS size influence on the gain of the preamplifier. We have changed the values of W and L of NMOS and PMOS and observed the change of the gain. Fig.27 shows the relationship between the preamplifier gain and the tail current source value. Fig.28 shows the relationship between the preamplifier gain and NMOS W / L. Fig.29. shows the relationship between the preamplifier gain and PMOS2 W / L. Fig.30. shows the relationship between the preamplifier gain and PMOS1 W / L.

Fig.27. Relationship between preamplifier gain and tail current source value.

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Fig.28. Relationship between preamplifier gain and NMOS W / L.

Fig.29. Relationship between preamplifier gain and PMOS2 W / L.

Fig.30. Relationship between preamplifier gain and PMOS1 W / L

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3.3 Charge-Domain Folding ADC

The circuits, operations and SPICE simulation results for G4, G3, G2, G1, G0 generation are shown in Fig. 30, 31, 32, 33 ,34 and 35, respectively. In phase 1, the output of each preamplifier is sampled and stored in each capacitor. In phase 2, the preamplifier output and the capacitor are disconnected. Then each capacitor is connected. Notice that the differential capacitor outputs are connected alternately (Fig.

25). It is analog encoding in charge domain and discrete-time, which is suitable for CMOS implementation. In other words, analog encoding is done by just connection, and hence it reduces hardware and power significantly compared to the flash ADC.

This can avoid CMOS low current drivability. Its conversion latency is one or two- clock periods, which is comparable to the flash ADC. If this ADC is used stand alone, it may suffer from device mismatches such as preamplifier and comparator offsets, which lead to the whole ΔΣ ADC nonlinearity. However, it is used inside the modulator, the nonlinearity is noise-shaped and does not affect the whole modulator linearity significantly (Fig. 36).

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(a) circuit.

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(c) Power consumption of G5.

Fig. 30. Generation circuit of the proposed charge-domain folding ADC for G5.

(a) circuit

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(b) SPICE simulation result.

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(a) circuit

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(a) circuit

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(a) circuit

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(a) circuit

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Fig. 36. Explanation of analog encoding for G3 generation.

3.4 Comparator

The comparator compares two or more data items to determine whether they are

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called a comparator. The comparator is a circuit that compares an analog voltage signal with a reference voltage. The two inputs of the comparator are analog signals, and the output is a binary signal 0 or 1. When the difference of the input voltage increases or decreases and the sign of the positive and negative remains unchanged, the output remains constant.

We used comparator that is LT1716 comparator. LT1716 comparator operates on any total power supply voltage between 2.7V and 44V drawing 35µA of quiescent current.

The LT1716 has a unique input stage that can be taken 44V above V–, independent of V+ supply. (Built-in resistors protect the inputs for faults below the negative supply of up to 5V.) The inputs can withstand 44V both differential and common mode. The output stage includes a class “B” pull-up current source, eliminating the need for an external resistive pull-up and saving power. Output voltage swings to within 35mV of the negative supply and 55mV of the positive supply, which makes the comparator a good choice for low voltage single supply operation. The output stage is also designed to drive loads connected to a higher supply than the LT1716 supply, the same as an open collector output stage.

3.5 Application

Now, let us discuss the power issue which VLSI chips face due to high device density and high operating frequency. It is important because of proliferation of portable consumer electronics and concerns on environments and energy sources, and hence low

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power is crucial also for ADC. ADC chip area has been becoming more and more small due to low cost and useless power reduction by hardware; chip area has shrunk by 100 times in 25 years for the same performance ADC.

Let us compare with a flash ADC in 6-bit case. The 6-bit flash ADC has 63 preamplifiers, 63 comparators and a digital encoder. The 6-bit charge-domain Folding ADC have 68 preamplifiers, 6 comparators and a switched capacitor array. So, the charge-domain folding ADC needs only small chip area and low power, which improves ADC Figure of Merit (FOM) significantly.

The advantages of the charge domain folding ADC are high speed, low power and small chip area, whereas its disadvantage is overall ADC nonlinearity due to device mismatch. The proposed killer application is its usage inside a multi-bit ΔΣ ADC. There, currently a 3-bit flash ADC is used, however we consider that a 6-bit folding ADC can be used, thanks to its small chip area and low power. Its nonlinearity is noise-shaped inside the modulator. See Fig.37.

Fig. 37. Charge domain folding ADC usage inside a multi-bit ΔΣ AD modulator.

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4. Conclusion and Discussion

4.1 Discussion

MOSFET characteristics variations are relatively large, and the designed folding ADC does not employ the offset cancellation circuits in the preamplifier, the folding circuits and comparators. Then the overall nonlinearity of the ADC would be large, even though it can be fast, small circuit and low power. Then we consider use it inside the multi-bit AD modulator [9]. There, the internal multi-bit ADC needs the following:

[10, 11]

(1) High speed (2) Low power (3) Small circuits

However, its overall nonlinearities do not matter because they are noise-shaped and do not affect the signal band.

The conventional flash-type can be used for 3-bit or 4-bit internal ADC, however our proposed folding ADC can be used up-to 6-bit. This can realize a new architecture for the multi-bit ΔΣ AD modulator [11, 12].

4.2. Conclusion

In this paper, usage of the folding ADC inside the multi-bit ΔΣ AD modulator is investigated; the 6-bit resolution ADC inside the modulator can be realized with small

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latency and small circuitry as well low power. Finally, we remark that the folding ADC can be also used inside the pipelined ADC with the similar arguments as the contents described in this paper.

A CMOS charge-domain folding A-D conversion circuit that performs analog encoding in a charge mode suitable for realization in CMOS is considered and its simulation operation is confirmed. A preamplifier is designed in the first stage, and its saturation characteristics are used to realize analog encoding in the calculation in the switched capacitor circuit. This configuration is suitable for easily realizing 5-bit or 6- bit ADC in a high-speed, low-consumption stand-alone A-D converter or an internal ADC of a multi-bit ΔΣ AD modulator.

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Kuwana, H. Kobayashi, "Folding ADC for Multi-bit ΔΣ AD Modulator". International Conference on Analog VLSI Circuits 2021 (AVIC 2021), Bordeaux, France, (October.18- 21,2021) submitted

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[14] Samer Medawar, Peter Händel, Senior Member, IEEE, Niclas Björsell, Member, IEEE,and Magnus Jansson, Member, IEEE, “Input-Dependent Integral Nonlinearity Modeling for Pipelined Analog–Digital Converters (Nov. 2010).

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Acknowledgments

I would like to express my deepest gratitude to Professor Haruo Kobayashi for his encouraging guidance and encouragement in my research and life. Thanks to assistant professor Anna Kuwana for providing support during my research and helping me a lot in past years.

I would also like to thank Professor Kuniyuki Motojima and Associate Professor Yasushi Yuminaka. I sincerely thank all my friends.

Peace begins with a smile.

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List of Publications

[1] Xiongyan Li, Haijun Lin, Anna Kuwana, Haruo Kobayashi, "Charge-Domain Folding Analog-to-Digital Converter". 11th Institute of Electrical Engineers of Japan (IEEJ 2020), Gunma and Tochigi, Japan (Mar. 1-2, 2021)

[2]Xiongyan Li, Tianrui Feng, Lengkhang Nengvang, Shogo Katayama, Jianglin Wei, Haijun Lin, Kazufumi Naganuma, Kiyoshi Sasai, Junichi Saito, Anna Kuwana, Haruo Kobayashi,

"Folding ADC for Multi-bit ΔΣ AD Modulator". International Conference on Analog VLSI Circuits 2021 (AVIC 2021), Bordeaux, France (October.18-21,2021)

[3] Xiongyan Li, Anna Kuwana, Haruo Kobayashi, "Small Awareness of Commonality Between Modern Technology and Wasan- Electronic Circuit Design and Casting Out Nine, Casting Out Eleven", Wasan Journal, vol. 54, No.4, pp. 46-51 (2020).

李雄炎、桑名杏奈、小林春夫「現代技術のベースになる数学と和算の共通性の小さな気付き－電子回路設計と 9 去法,11 去法－」和算ジャーナル第４号 (会報通巻 54), pp.46-51 (2020年).

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