 2 High frequency trench capacitors

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A LOW SERIES RESISTANCE, HIGH DENSITY, TRENCH CAPACITOR FOR ,

HIGH-FREQUENCY APPLICATIONS

Gordon Grivna, Sudhama Shastri, Yujing Wu, & Will Cai

Sept, 2008

www.onsemi.com

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Presentation Outline

 1 I t d ti /

 1. Introduction / purpose

 2. High frequency trench capacitors a) MIS trench capacitors

a) MIS trench capacitors

b) High frequency “wrap-around” PIP cap.

 3. High frequency PIP capacitor characterizationg q y p a) Electrical characterization and modeling b) Reliability evaluation

 4. Potential enhancements / applications

 5. Summary

 6 A k l d

 6. Acknowledgments

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1. Introduction/Purpose

 A novel, modular, high speed, VLSI MOS-compatible decoupling trench capacitor with tunable frequency decoupling trench capacitor with tunable frequency response has been modeled and electrically

characterized.

 The flexible capacitor design enables low Dt, drop-in capability across a number of technologies and has capability across a number of technologies and has been qualified for both CMOS and BiCMOS

applications.

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 2 High frequency trench capacitors

 2. High frequency trench capacitors

) MIS t h it

a) MIS trench capacitors

“Typical” MIS trench bypass capacitors suffer from large series resistance and consequent poor

frequency response.

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MIS Trench Capacitors

Structure of “typical” MIS type bypass trench capacitor with implanted bottom plate

AlSi 40KA

TRENCH CAPACITOR

SINGLE DIODE POLYSILICON RESISTOR

BOTTOM PLATE

P+ Well

TOP PLATE

N Epi N+

P+ P+

PLATE PLATE

TOP PLATE

HIGH RESISTANCE

LOWER PLATE CONNECT N Epi

P+ POLY

400A

NITRIDE DIELECTRIC P+ POLY

TOP ELECTRODE

.005 Ohm-cm Boron Substrate

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MIS Trench Capacitors

Structure of high density RF MIS trench capacitor with laterally diffused bottom plate

(E t t d f F R b t l I t ti l Mi l t i d P k i S i t 2001 ) (Extracted from F. Roozeboom et. al. -International Microelectronics and Packaging Society, 2001 )

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MIS Trench Capacitors

 Diffused bottom plate trench capacitors lose their effectiveness as the capacitance per unit area

increases, since the bottom plate resistance can increases, since the bottom plate resistance can become prohibitively large.

 As trench depth and capacitance per unit area increase further, low resistance access to the bottom plate becomes critical for high speed bottom plate becomes critical for high speed applications.

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MIS Trench Capacitors

Trench Capacitor Device Suitable for Decoupling Applications in High-Frequency Operation

Extracted from International Patent Publication Number WO 2007/054870 A1, May 2007

Bottom plate backside contact contact

Top plate frontside contact contact

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2. High frequency trench capacitors 2. High frequency trench capacitors

a) MIS trench capacitors

b) High frequency “wrap-around”

PIP capacitor

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“Wrap-Around” PIP Capacitor

X-section view of “wrap-around” PIP capacitor for on-chip bypass and tuning applications

N-

I N+

P+ Substrate Trench Bottom

Contact Substrate contact

or isolation trench

Bottom plate contact trench

PIP capacitor

“finger”

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“Wrap-Around” PIP Capacitor

Diffusion model of trench bottom plate

 The use of a highly- doped bottom liner

N+ EPI

doped bottom liner poly electrode and the consequent

outdiffusion makes this

i f i

capacitor function even in the presence of

highly-doped buried layers which may

P+ Substrate

layers which may

otherwise “break” the connection of the

bottom electrode.

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“Wrap-Around” PIP Capacitor

X-section view of “wrap-around” PIP cap

top plate contact contact trench/bottom

plate contact

l top plate dielectric layer

contact trench capacitor trench

bottom plate

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“Wrap-Around” PIP Capacitor

X-section drawing of “wrap-around” PIP capacitor in lightly doped substrate

N-

Reduced resistance to bottom plate

P- Substrate

Substrate contact or isolation trench

PIP capacitor

“finger”

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“Wrap-Around” PIP Capacitor

X-section SEM of “wrap-around” PIP capacitor in lightly doped substrate

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“Wrap-Around” PIP Capacitor

 The addition of a separate bottom plate enables “drop- i ” bilit

Top Plate

in” capability

irrespective of the substrate doping type EPI layers

Bottom plate

type, EPI layers, thermal budget, or substrate dielectric layers

Capacitor Dielectric

P i

layers. Previous

Silicon top structure

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3 Hi h f PIP it

3. High frequency PIP capacitor characterization

a) Electrical characterization and ) modeling

b) Reliability evaluation

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Electrical Characterization

Leakage comparison of MIS cap (no liner) on bare silicon substrate to PIP cap with bottom polysilicon liner

Current Vs Voltage

1 0E 07 1.0E-06

1 0E 09 1.0E-08 1.0E-07

C t

1 0E 11 1.0E-10 1.0E-09

wfr 1, no liner wfr 5, no liner wfr 2, 500A wfr 4 500A Current

(Amps)

1.0E-13 1.0E-12

1.0E-11 wfr 4, 500A

wfr 3, 1700A wfr 6, 1700A

1.0E 13

0 2 4 6 8 10 12 14 16 18 20

Voltage, Volt

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Electrical Characterization

Poly lined trench caps have improved linearity compared to standard MIS trench caps.

Capacitance Vs Applied Voltage

11.0

p p

10.0 10.5

/um2

8 5 9.0 9.5

Capacitance, fF/

wfr 1, no liner wfr 5, no liner

7.5 8.0

8.5 wfr 2, 500A

wfr 4, 500A wfr 3, 1700A wfr 6, 1700A

0 1 2 3 4 5 6 7 8 9 10

Voltage, volt

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Electrical Characterization

High linearity, g y, good across- wafer

uniformity uniformity (±1.25%)

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Electrical Characterization

Low leakage, excellent linearity over temperature

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Device Modeling

Layout n

_f

=5, n

_p

=2

Cross-section Cross section n

f (fingers)

=3,

n =2

n

p (modules in parallel)

=2

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Device Modeling

Very High Frequency Capacitor Layout n

_f

=2, n

_p

=20

Capacitor Trench

Substrate Contact Trench Isolation Trench

y

_f _p

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Device Modeling

Reduced Frequency Capacitor for audio-band filter chip

n =16 n =1

n

_f

=16, n

_p

=1

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Device Modeling

Di t ib t d R C Distributed R-C model for n_f=2, N_V=6. Metal

inductance is

optionally added.

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Device Modeling

 C_eff=Im(Yij)/(2f), is the effective

it

capacitance

extracted from Y- parameters; it

includes the effect of series resistance

 N_V~8 is sufficient for the model, that is, eight vertical sections are

enough for enough for

ensuring accuracy

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Device Modeling

 A given target capacitance is obtained by a combination of fingers and parallel sections.

 The lower n_f is, the better is the frequency response.

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Model-Extraction

 Pseudo-2D treatment is valid for the widths under consideration consideration

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Model Extraction

 A low-frequency fit is first obtained: only 1-2 parameters are tweaked; the rest are geometry-based

 Y t bt i d f LCR t d S t A l

 Y-parameters obtained from LCR meter and Spectrum Analyzer

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Model Extraction

nf=40, np=1

nf=4, np=10 , p

 RF parameter extraction requires S-parameter data from 2-port GSG measurements

 Device asymmetry can predicted using lumped element model

 Correctly modeling substrate resistance is very important

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3 Hi h f PIP it

3. High frequency PIP capacitor characterization

a) Electrical characterization and ) modeling

b) Reliability evaluation

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Reliability Evaluation

TEM Construction Analysis

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Reliability Evaluation

TEM Evaluation of Capacitor Dielectric

Trench Bottom Trench Bottom “Corner”

Trench Sidewall

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Reliability Evaluation

Lognormal Distributions of Intrinsic TDDB Failures of Intrinsic TDDB Failures

Capacitor data

With Individual Lognormal MLE's Lognormal Probability Plot

16 5

7 .8 .9 .95

.98 4.5MV.per.cm

4.75MV.per.cm 5MV.per.cm

.2 .3 .4 .5 .6 .7

Fraction Failing

.005 .01 .02 .05 .1

Hours

2 5 10 20 50 100 200 500

Wed Sep 29 17:26:41 2004

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Reliability Evaluation

Maximum Likelihood Fit

Extrapolation to 10 V @ 150 °C

.9999

Capacitor data

with Lognormal Linear Model MLE Lognormal Probability Plot

4.5MV.per.cm

.8 .9 .95 .98 .995 .999

ng

4.5MV.per.cm 4.75MV.per.cm 5MV.per.cm 2 MV.per.cm

01 .05 .1 .2 .4 .6

Fraction Faili

.000003 .00005 .0005 .002 .01

10^00 10^01 10^02 10^03 10^04 10^05 10^06 10^07 10^08 10^09 10^10

Hours

10^00 10^01 10^02 10^03 10^04 10^05 10^06 10^07 10^08 10^09 10^10

Wed Sep 29 18:23:35 2004

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Reliability Evaluation

Lifetime Estimates 10 V @ 150 °C

•Quantile Estimates

F C it d t t 2 MV 7,895

•From Capacitor data at 2 MV.per.cm

•Lognormal MLE and Pointwise Approximate 90% Confidence Intervals

• p Quanhat Std.Err. 90% Lower 90% Upper

7,895 years

• 0.001 193509360 121049290 69157870 5.415e+008

• 0.005 265309753 165510803 95085143 7.403e+008

• 0.010 309187546 192684448 110928051 8.618e+008

• 0.050 469668005 292159050 168820772 1.307e+009

• 0.100 586927866 364961308 211052126 1.632e+009

• 0.200 768766377 478075427 276413038 2.138e+009

• 0.300 933922386 581039386 335643103 2.599e+009

• 0.400 1102876638 686586047 396108502 3.071e+009

• 0.500 1288325603 802673961 462337302 3.590e+009

• 0.600 1504957855 938577225 539528708 4.198e+009

• 0.700 1777217127 1109797762 636294633 4.964e+009

• 0 8000.800 21590211412159021141 13506321421350632142 771571247771571247 6 041e+0096.041e+009

• 0.900 2827916269 1774365391 1007511006 7.937e+009

• 0.990 5368207358 3399989142 1894045950 1.521e+010

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L l Di t ib ti

Reliability Evaluation

Lognormal Distributions

Extrinsic Failure Mode Evident

Capacitor data

.95 .98

Capacitor data

With Individual Lognormal MLE's Lognormal Probability Plot

4.5MV.per.cm 4.75MV.per.cm 5MV.per.cm

16 5

.5 .6 .7 .8 .9

Failing

5MV.per.cm

05 .1 .2 .3 .4 .5

Fraction F

.005 .01 .02 .05

0.5 1.0 2.0 5.0 10.0 20.0 50.0 100.0 200.0 500.0

Extrinsic

Hours Wed Sep 29 16:42:35 2004

Failures

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Reliability Evaluation

Capacitor dielectric thinning on top surface after

poly etchback found as source for extrinsic failures

Nitride~230A

Nitride on trench sidewall Top nitride after polysilicon etchback

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4. Potential enhancements

and applications

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Enhancements

Multi-use trench process: isolation, oxide termination, substrate contact, bottom plate contact

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Enhancements

Oxide lined t h ith trench with

substrate contact opening

opening

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Enhancements

Optical X-section view of oxide lined trenches with substrate contact

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Enhancements

Oxide isolated substrate contacts

SEM Highlighting deep polysilicon contact SEM highlighting dopant outdiffusion SEM Highlighting deep polysilicon contact SEM highlighting dopant outdiffusion

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Enhancements

Oxide isolated substrate contacts

Boron doped poly fill Phosphorous doped poly fill

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Enhancements

Insitu doped trench (post 1100C 45min anneal)p (p )

Boron doped Phos doped

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Enhancements

Extreme trench depth for very high capacitance on chip

capacitance on chip

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Enhancements

Potential for silicided bottom plate for further resistance reduction.

N-

P- Substrate

Substrate contact or isolation trench

PIP capacitor

“finger”

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5. Summary

 A high-performance trench capacitor has been integrated into RF BiCMOS and other been integrated into RF BiCMOS and other technologies.

 A distributed trench-capacitor model has

been developed and implemented in SPICE

been developed and implemented in SPICE.

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Summary

 M d l h b f ll d i

 Models have been successfully used in several high-frequency designs.

Capacitor has been successfully added to multiple substrates and process integrations multiple substrates and process integrations.

Several potential enhancements have been

demonstrated.

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