Test Procedure for the NCP1362 HV
Evaluation Board
Board Electrical Schematic
Ac input voltage
Dc output voltage
VCC R29
240k
SOIC8
R31 NTC
f ault
R11 15V/SOD323 C6
2u2 D6
P6SMB120AT3G DO-214AA
D1 MURA230T3G
C14 1n
0
0 Bulk/2
Vcc
DRV + C4
10u/400V
C21 100n / X2
R39 1M R17
470k
R40 2M2
C16 22pF D5
18V
COUT1 470u/16V DB1
MDB10SS-Micro DIP + 1
- 2 3 AC2
4 AC1
R18 47k C3
100n / X2
RS1 1.3 R6 0
CS
RS2 3 R41
NC
M2
FQU2N100TU-IPAK
R37 3M3 R8
5R
COUT3 47uF
Comp
0
0
Bulk
Gate
v s_zcd Aux
C10 1nF
C19 0R
R30 1k2
IC1
NCP1362 VS/ZCD 1
FB 2
FAULT 3 4 CS
DRV 5 GND 6 VCC 7 BO/LFF 8
C7 100pF / Y 1 CM1
2.2mH 1
2 3
4
R15 470k ph1
ph2
R38 470k
0
0
Vcc
DRV
Bulk/2 R33
470k
R14 470k
COUT2 470u/16V L1 220uH
+ C18 10u/400V
R28 82k J1
PM5.08/2 1 2
R24 4k3
R16 10R
R25 3M3 C2
100pF/250V
R19 3M3 R10
0R
C12 4n7
D4 MMSD4148T1 v p
C15 100nF +
C17 10u/400V
0
0 AC
ISense
Vcc
T1 XFMR_PSR 4
1
9
6 2
3 5
8
7 R9
47k
C9 4.7pF
R4 47k
L2 1uH +
C5 10u/400V
D3 BAS21
C11 4u7 R34
470k
D2 US1MFA
0
ROUT1 0
0
Aux
Source
ISense DRV
GND
R22 10k
J2 PM5.08/2 1 2