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Synchronous Buck Controller
ADP3193A
©2008 SCILLC. All rights reserved. Publication Order Number:
FEATURES
Selectable 2- or 3-phase operation at up to 1 MHz per phase
±7.7 mV worst-case differential sensing error over temperature
Logic-level PWM outputs for interface to external high power drivers
Fast enhanced PWM (FEPWM) flex mode for excellent load transient performance
Active current balancing between all output phases Built-in power-good/crowbar blanking supports on-the-fly
VID code changes
Digitally programmable 0.5 V to 1.6 V output supports both VR10.x and VR11 specifications
Programmable short-circuit protection with programmable latch-off delay
APPLICATIONS
Desktop PC power supplies for Next generation Intel® processors VRM modules
GENERAL DESCRIPTION
The ADP3193A1 is a highly efficient, multiphase, synchronous buck switching regulator controller optimized for converting a 12 V main supply into the core supply voltage required by high performance Intel processors. It uses an internal 8-bit DAC to read a voltage identification (VID) code directly from the processor, which is used to set the output voltage between 0.5 V and 1.6 V.
This device uses a multimode PWM architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for VR size and efficiency. The phase relation- ship of the output signals can be programmed to provide 2- or 3-phase operation, allowing for the construction of up to three complementary buck switching stages.
The ADP3193A also includes programmable no load offset and slope functions to adjust the output voltage as a function of the load current, optimally positioning it for a system transient. The ADP3193A also provides accurate and reliable short-circuit protection, adjustable current limiting, and delayed power-good output that accommodates on-the-fly output voltage changes requested by the CPU.
1 Protected by U.S. Patent Number 6,683,441; other patents pending.
FUNCTIONAL BLOCK DIAGRAM
SHUNT REGULATOR
VC DAC +150mVDAC
850mV
–350mVDAC CSREF
2-/3-PHASE DRIVER LOGIC
EN 14 SET
1
2
8
7
16
5
3
32 – +
– + – + SHUTDOWNUVLO
15
22
21
20
19 18 17 13 11 12
4
6 VOLTAGEBOOT SOFT STARTAND
CONTROL DELAY
RESET
RESET
RESET
VID7 24
VID6 25
VID5 26
VID4 27
VID3 28
VID2 29
VID1 30
VID0 31
ADP3193A
+ CMP–
+ CMP–
+ CMP–
CROWBAR
CURRENT LIMIT
CURRENT MEASUREMENT
AND LIMIT
PRECISION REFERENCE
23 9 10
+ –
+ –
– + GND
EN
DELAY ILIMIT PWRGD
COMP
FBRTN
VIDSEL IREF
PWM2 PWM3
SW3 SW2 SW1
CSREF CSCOMP
CSSUM
FB PWM1
SS OD VCC RTRAMPADJ
CURRENT BALANCING CIRCUIT OSCILLATOR
06652-001
Figure 1.
The ADP3193A has a built-in shunt regulator that allows the part to be connected to the 12 V system supply through a series resistor.
The ADP3193A is specified over the extended commercial temperature range of 0°C to 85°C and is available in a 32-lead LFCSP.
TABLE OF CONTENTS
Features...1
Applications ...1
General Description...1
Functional Block Diagram...1
Revision History...2
Specifications ...3
Absolute Maximum Ratings ...5
ESD Caution ...5
Pin Configuration and Function Descriptions ...6
Typical Performance Characteristics...7
Test Circuits ...8
Theory of Operation...9
Start-Up Sequence ...9
Phase Detection Sequence ...9
Master Clock Frequency ...10
Output Voltage Differential Sensing ...10
Output Current Sensing ...10
Current Control Mode and Thermal Balance...10
Voltage Control Mode ...10
Current Reference ...11
Fast Enhanced PWM Mode...11
Delay Timer ...11
Soft Start ...11
Current-Limit, Short-Circuit, and Latch-Off Protection ...11
Dynamic VID ...12
Power-Good Monitoring ...12
Output Crowbar...12
Output Enable and UVLO...13
Application Information ...18
Setting the Clock Frequency ...18
Soft Start Delay Time ...18
Current-Limit Latch-Off Delay Times...18
Inductor Selection...18
Current Sense Amplifier ...19
Inductor DCR Temperature Correction...20
Output Offset...20
COUT Selection...21
Power MOSFETs ...22
Ramp Resistor Selection ...23
COMP Pin Ramp ...23
Current-Limit Setpoint ...23
Feedback Loop Compensation Design ...24
CIN Selection and Input Current di/dt Reduction ...25
Shunt Resistor Design ...25
Tuning Procedure for ADP3193A ...26
Layout and Component Placement...27
Outline Dimensions...29
Ordering Guide ...29
REVISION HISTORY
02/08—Rev 1: Conversion to ON Semiconductor 05/07—Revision 0: Initial Version
SPECIFICATIONS
VCC = 5 V, FBRTN = GND, TA = 0°C to 85°C, unless otherwise noted.1 Table 1.
Parameter Symbol Conditions Min Typ Max Unit
REFERENCE CURRENT
Reference Bias Voltage VIREF 1.5 V
Reference Bias Current IIREF RIREF = 100 kΩ 14.25 15 15.75 μA
ERROR AMPLIFIER
Output Voltage Range2 VCOMP 0 4.4 V
Accuracy VFB Relative to nominal DAC output, referenced to FBRTN (see Figure 4)
−7.7 +7.7 mV
VFB(BOOT) In startup 1.092 1.1 1.108 V
Differential Nonlinearity −1 +1 LSB
Input Bias Current IFB IFB = IIREF 13.5 15 16.5 μA
FBRTN Current IFBRTN 65 200 μA
Output Current ICOMP FB forced to VOUT − 3% 500 μA
Gain Bandwidth Product GBW(ERR) COMP = FB 20 MHz
Slew Rate COMP = FB 25 V/μs
Boot Voltage Hold Time tBOOT CDELAY = 10 nF 2 ms
VID INPUTS
Input Low Voltage VIL(VID) VID(x), VIDSEL 0.4 V
Input High Voltage VIH(VID) VID(x), VIDSEL 0.8 V
Input Current IIN(VID) −1 μA
VID Transition Delay Time2 VID code change to FB change 400 ns No CPU Detection Turn-Off Delay Time2 VID code change to PWM going low 5 μs
OSCILLATOR
Frequency Range2 fOSC 0.25 4 MHz
Frequency Variation fPHASE TA = 25°C, RT = 210 kΩ, 3-phase 240 260 293 kHz TA = 25°C, RT = 100 kΩ, 3-phase 530 kHz TA = 25°C, RT = 40 kΩ, 3-phase 1000 kHz Output Voltage VRT RT = 243 kΩ to GND 1.9 2.0 2.1 V RAMPADJ Output Voltage VRAMPADJ RAMPADJ − FB −50 +50 mV
RAMPADJ Input Current Range IRAMPADJ 1 50 μA
CURRENT SENSE AMPLIFIER
Offset Voltage VOS(CSA) CSSUM − CSREF (see Figure 4) −1.0 +1.0 mV
Input Bias Current IBIAS(CSSUM) −10 +10 nA
Gain Bandwidth Product GBW(CSA) CSSUM = CSCOMP 10 MHz
Slew Rate CCSCOMP = 10 pF 10 V/μs
Input Common-Mode Range CSSUM and CSREF 0 3.5 V
Output Voltage Range 0.05 3.5 V
Output Current ICSCOMP 500 μA
Current Limit Latch-Off Delay Time tOC(DELAY) CDELAY = 10 nF 8 ms CURRENT BALANCE AMPLIFIER
Common-Mode Range VSW(x)CM −600 +200 mV
Input Resistance RSW(x) SW(x) = 0 V 10 17 26 kΩ
Input Current ISW(x) SW(x) = 0 V 8 12 20 μA
Input Current Matching ΔISW(x) SW(x) = 0 V −4 +4 %
Parameter Symbol Conditions Min Typ Max Unit CURRENT LIMIT COMPARATOR
ILIMIT Bias Current IILIMIT IILIMIT = 2/3 × IIREF 9 10 11 μA
ILIMIT Voltage VILIMIT RILIMIT = 121 kΩ (VILIMIT = (IILIMIT × RILIMIT)) 1.09 1.21 1.33 V
Maximum Output Voltage 3 V
Current-Limit Threshold Voltage VCL VCSREF − VCSCOMP, RILIMIT = 121 kΩ 80 100 125 mV
Current-Limit Setting Ratio VCL/VILIMIT 82.6 mV/V
DELAY TIMER
Normal Mode Output Current IDELAY IDELAY = IIREF 12 15 18 μA Output Current in Current Limit IDELAY(CL) IDELAY(CL) = 0.25 × IIREF 3.0 3.75 4.5 μA
Threshold Voltage VDELAY(TH) 1.6 1.7 1.8 V
SOFT START
Output Current ISS During startup, ISS = IIREF 12 15 18 μA
ENABLE INPUT
Threshold Voltage VTH(EN) 800 850 900 mV
Hysteresis VHYS(EN) 80 100 125 mV
Input Current IIN(EN) −1 μA
Delay Time tDELAY(EN) EN > 950 mV, CDELAY = 10 nF 2 ms
OD OUTPUT
Output Low Voltage VOL(OD) 160 500 mV
Output High Voltage VOH(OD) 4 5 V
POWER-GOOD COMPARATOR
Undervoltage Threshold VPWRGD(UV) Relative to nominal DAC output −400 −350 −300 mV Overvoltage Threshold VPWRGD(OV) Relative to nominal DAC output 100 150 200 mV Output Low Voltage VOL(PWRGD) IPWRGD(SINK) = −4 mA 150 300 mV
Power-Good Delay Time
During Soft Start2 CDELAY = 10 nF 2 ms
VID Code Changing 100 250 μs
VID Code Static 200 ns
Crowbar Trip Point VCROWBAR Relative to nominal DAC output 100 150 200 mV
Crowbar Reset Point Relative to FBRTN 320 375 430 mV
Crowbar Delay Time tCROWBAR Overvoltage to PWM going low
VID Code Changing 100 250 μs
VID Code Static 400 ns
PWM OUTPUTS
Output Low Voltage VOL(PWM) IPWM(SINK) = −400 μA 160 500 mV Output High Voltage VOH(PWM) IPWM(SOURCE) = 400 μA 4.0 5 V SUPPLY VSYSTEM = 12 V, RSHUNT = 340 Ω (see Figure 4)
VCC2 VCC 4.65 5 5.55 V
DC Supply Current IVCC VSYSTEM = 13.2 V, RSHUNT = 340 Ω 25 mA
UVLO Turn-On Current 6.5 11 mA
UVLO Threshold Voltage VUVLO VCC rising 9 V
UVLO Turn-Off Voltage VCC falling 4.1 V
1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
2 Guaranteed by design or bench characterization, not tested in production.
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
VCC −0.3 V to +6 V
FBRTN −0.3 V to +0.3 V
PWM1 to PWM3, RAMPADJ −0.3 V to VCC + 0.3 V SW1 to SW3 −5 V to +25 V
<200 ns −10 V to +25 V All Other Inputs and Outputs −0.3 V to VCC + 0.3 V Storage Temperature Range −65°C to +150°C Operating Ambient Temperature Range 0°C to 85°C Operating Junction Temperature 125°C Thermal Impedance (θJA) 32.6°C/W Lead Temperature
Soldering (10 sec) 300°C Infrared (15 sec) 260°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all other voltages are referenced to GND.
ESD CAUTION
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1 INDICATOR 1
EN 2 PWRGD
3 FBRTN
4 FB
5 COMP
6 SS
7 DELAY
8 ILIMIT
24 VID7 23 VCC 22 PWM1 21 PWM2 20 PWM3 19 SW1 18 SW2 17 SW3 9RT 10RAMPADJ 11CSREF 12CSSUM 13CSCOMP 14GND 15OD 16IREF
32VIDSEL 31VID0 30VID1 29VID2 28VID3 27VID4 26VID5 25VID6
ADP3193A
TOP VIEW (Not to Scale)
NOTES
1. THE EXPOSED EPAD ON BOTTOM SIDE OF PACKAGE IS AN ELECTRICAL CONNECTION AND SHOULD BE SOLDERED TO GROUND.
06652-005
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions Pin No. Mnemonic Description
1 EN Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low.
2 PWRGD Power-Good Output. Open-drain output that signals when the output voltage is outside of the proper operating range.
3 FBRTN Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage.
4 FB Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor between this pin and the output voltage sets the no load offset point.
5 COMP Error Amplifier Output and Compensation Point.
6 SS Soft Start Delay Setting Input. An external capacitor connected between this pin and GND sets the soft start ramp-up time.
7 DELAY Delay Timer Setting Input. An external capacitor connected between this pin and GND sets the overcurrent latch-off delay time, boot voltage hold time, EN delay time, and PWRGD delay time.
8 ILIMIT Current-Limit Set Point. An external resistor from this pin to GND sets the current-limit threshold of the converter.
9 RT Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator frequency of the device.
10 RAMPADJ PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal PWM ramp.
11 CSREF Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense amplifier and the power-good and crowbar functions. This pin should be connected to the common point of the output inductors.
12 CSSUM Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor currents to measure the total output current.
13 CSCOMP Current Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determines the gain of the current sense amplifier and the positioning loop response time.
14 GND Ground. All internal biasing and the logic output signals of the device are referenced to this ground.
15 OD Output Disable Logic Output. This pin is actively pulled low when the EN input is low or when VCC is below its UVLO threshold to signal to the driver IC that the driver high-side and low-side outputs should go low.
16 IREF Current Reference Input. An external resistor from this pin to ground sets the reference current for IFB, IDELAY, ISS, and IILIMIT. 17 to 19 SW3 to SW1 Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases should be
left open.
20 to 22 PWM3 to PWM1 Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver, such as the ADP3120A.
Connecting PWM3 output to VCC causes that phase to turn off, allowing the ADP3193A to operate as a 2- or 3-phase controller.
23 VCC Supply Voltage. A 340 Ω resistor should be placed between the 12 V system supply and the VCC pin. The internal shunt regulator maintains VCC = 5 V.
24 to 31 VID7 to VID0 Voltage Identification DAC Inputs. These eight pins are pulled down to GND, providing a logic zero if left open. When in normal operation mode, the DAC output programs the FB regulation voltage from 0.5 V to 1.6 V (see Table 4).
32 VIDSEL VID DAC Selection Pin. The logic state of this pin determines whether the internal VID DAC decodes VID0 to VID7 as extended VR10 or VR11 inputs.
TYPICAL PERFORMANCE CHARACTERISTICS
6000
013
RT(kΩ)
FREQUENCY (kHz)
5000
4000
3000
2000
1000
27 39 50 68 82 130 210 248 270 430 742 850 MASTER CLOCK
06652-017
Figure 3. Master Clock Frequency vs. RT
TEST CIRCUITS
1.25V
8-BIT CODE
1kΩ 1
32
1μF 100nF
100nF 20kΩ 10nF
10nF
100kΩ
12V
680Ω 680Ω +
250kΩ
VID7 PWM1VCC PWM2 PWM3SW1 SW2 SW3
VIDSEL VID0 VID1 VID2 VID3 VID4 VID5 VID6
RT RAM
PADJ CSREF CSSUM CSCOMP GND
OD IREF
EN PWRGD FBRTN FB COMPSS DELAY ILIMIT
ADP3193A
06652-002
Figure 4. Closed-Loop Output Voltage Accuracy
CSSUM 13
CSCOMP
12 23
VCC
CSREF 11
GND 14 39kΩ
680Ω 680Ω
100nF
1kΩ
1V
ADP3193A
VOS = CSCOMP – 1V40 12V
06652-003
Figure 5. Current Sense Amplifier Offset Voltage (VOS)
23 VCC
10kΩ
1V
ADP3193A
680Ω 680Ω
12V
+ 5
COMP
4 FB
11 CSREF
14 GND
DACVID
06652-004
Figure 6. Positioning Voltage
THEORY OF OPERATION
The ADP3193A combines a multimode, fixed-frequency PWM control with multiphase logic outputs for use in 2- and 3-phase synchronous buck CPU core supply power converters. The internal VID DAC is designed to interface with the Intel 8-bit VRD/VRM 11 and 7-bit VRD/VRM 10.x CPUs. Multiphase operation is impor- tant for producing the high currents and low voltages demanded by today’s microprocessors. Handling the high currents in a single- phase converter increases thermal demands on the components in the system, such as the inductors and MOSFETs.
The multimode control of the ADP3193A ensures a stable, high performance topology for the following:
• Balancing currents and thermals between phases
• High speed response at the lowest possible switching frequency and output decoupling
• Minimizing thermal switching losses by using lower frequency operation
• Tight load line regulation and accuracy
• High current output due to 3-phase operation
• Reduced output ripple due to multiphase cancellation
• PC board layout noise immunity
• Ease of use and design due to independent component selection
• Flexibility in design by allowing optimization for either low cost or high performance
START-UP SEQUENCE
The ADP3193A follows the VR11 start-up sequence shown in Figure 7. After both the EN and UVLO conditions are met, the DELAY pin goes through one cycle (TD1). The first three clock cycles of TD2 are blanked from the PWM outputs and used for phase detection, as explained in the Phase Detection Sequence section. Then, the soft start ramp is enabled (TD2), and the output increases to the boot voltage of 1.1 V. The boot hold time is determined by the DELAY pin as it goes through a second cycle (TD3). During TD3, the processor VID pins settle to the required VID code. When TD3 is over, the ADP3193A soft starts either up or down to the final VID voltage (TD4).
After TD4 has been completed and the PWRGD masking time (equal to VID on-the-fly masking) is completed, a third ramp on the DELAY pin sets the PWRGD blanking (TD5).
TD1
TD3
TD2
50μs TD5
TD4 SS
SUPPLY5V
VTT I/O (ADP3193A EN)
DELAY
VCC_CORE
VR READY (ADP3193A PWRGD)
VID INPUTSCPU VID INVALID VID VALID VBOOT
(1.1V) VBOOT (1.1V) UVLOTHRESHOLD
0.85V
VVID VVID 1V
VDELAY(TH) (1.7V)
06652-006
Figure 7. System Start-Up Sequence
PHASE DETECTION SEQUENCE
During startup, the number of operational phases and their phase relationship is determined by the internal circuitry that monitors the PWM outputs. Normally, the ADP3193A operates as a 3-phase PWM controller. Connecting the PWM3 pin to VCC programs 2-phase operation.
Prior to soft start, while EN is low, the PWM3 pin sinks approxi- mately 100 μA. An internal comparator checks the voltage on PWM3 and compares it with a threshold of 3 V. If the pin is tied to VCC, it is above the threshold. Otherwise, an internal current sink pulls the pin to GND, which is below the
threshold. PWM1 and PWM2 are low during the phase detection interval that occurs during the first three clock cycles of TD2. After this time, if PWM3 is not pulled to VCC, the 100 μA current sink is removed, and it functions as normal PWM output. If PWM3 is pulled to VCC, the 100 μA current source is removed, and it is put into a high impedance state.
The PWM outputs are logic-level devices intended for driving external gate drivers such as the ADP3120A. Because each phase is monitored independently, operation approaching 100% duty cycle is possible. In addition, more than one output can be on at the same time to allow overlapping phases.
MASTER CLOCK FREQUENCY
The clock frequency of the ADP3193A is set with an external resistor connected from the RT pin to ground. The frequency follows the graph in Figure 3. To determine the frequency per phase, the clock is divided by the number of phases in use. If all phases are in use, divide by 3. If PWM3 is tied to VCC, divide the master clock by 2 for the frequency of the remaining phases.
OUTPUT VOLTAGE DIFFERENTIAL SENSING
The ADP3193A includes differential sensing, high accuracy VID DAC and reference, and a low offset error amplifier. This maintains a worst-case specification of ±7.7 mV differential sensing error over its full operating output voltage and temperature range. The output voltage is sensed between the FB pin and the FBRTN pin. FB should be connected through a resistor to the regulation point, usually the remote sensing pin of the micro- processor. FBRTN should be connected directly to the remote sensing ground point. The internal VID DAC and precision reference are referenced to FBRTN, which has a minimal current of 65 μA to allow accurate remote sensing. The internal error amplifier compares the output of the DAC to the FB pin to regulate the output voltage.OUTPUT CURRENT SENSING
The ADP3193A provides a dedicated current sense amplifier (CSA) to monitor the total output current for proper voltage positioning vs. load current and for current-limit detection.
Sensing the load current at the output gives the total average current being delivered to the load, which is an inherently more accurate method than peak current detection or sampling the current across a sensing element, such as the low-side MOSFET.
Depending on the objectives of the system, this amplifier can be configured in several ways:
• Output inductor DCR sensing without a thermistor for lowest cost.
• Output inductor DCR sensing with a thermistor for improved accuracy in tracking inductor temperature.
• Sensing resistor for highest accuracy measurements.
The positive input of the CSA is connected to the CSREF pin, which is connected to the output voltage. The inputs to the amplifier are summed together through resistors from the sensing element, such as the switch node side of the output inductors,
to the inverting input CSSUM. The feedback resistor between CSCOMP and CSSUM sets the gain of the amplifier, and a filter capacitor is placed in parallel with this resistor. The gain of the amplifier is programmable by adjusting the feedback resistor.
The difference between CSREF and CSCOMP is also used as a differential input for the current-limit comparator.
To provide the best accuracy for sensing current, the CSA has a low offset input voltage and the sensing gain is set by the external resistor.
CURRENT CONTROL MODE AND THERMAL BALANCE
The ADP3193A has individual inputs (SW1 to SW3) for each phase that are used to monitor the current. This information is combined with an internal ramp to create a current-balancing feedback system that has been optimized for initial current balance accuracy and dynamic thermal balancing during operation. This current balance information is independent of the average output current information used for positioning, as described in the Output Current Sensing section.
The magnitude of the internal ramp can be set to optimize the transient response of the system. It also monitors the supply voltage for feedforward control for changes in the supply. A resistor connected from the power input voltage to the RAMPADJ pin determines the slope of the internal PWM ramp. External resistors can be placed in series with individual phases to create an inten- tional current imbalance, such as when one phase has better cooling and can support higher currents. Resistors RSW1 through RSW3 (see Figure 10) can be used for adjusting thermal balance in this 3-phase example. It is best to have the ability to add these resistors during the initial design; therefore, ensure that place- holders are provided in the layout.
To increase the current in any given phase, enlarge RSW for that phase (make RSW = 0 for the hottest phase, and do not change it during balancing). Increasing RSW to only 500 Ω results in a substantial increase in phase current. Increase each RSW value by small amounts to achieve balance, starting with the coolest phase first.
VOLTAGE CONTROL MODE
A high gain, high bandwidth voltage mode error amplifier is used for the voltage mode control loop. The control input voltage to the positive input is set via the VID logic according to the voltages listed in Table 4.
This voltage is also offset by the droop voltage for active positioning of the output voltage as a function of current, commonly known as active voltage positioning. The output of the amplifier is the COMP pin, which sets the termination voltage for the internal PWM ramps.
The negative input (FB) is tied to the output sense location with Resistor RB and is used for sensing and controlling the output voltage at this point. A current source (equal to IREF) from the FB pin flowing through RB is used for setting the no load offset voltage from the VID voltage. The no load voltage is negative with
respect to the VID DAC. The main loop compensation is incor- porated into the feedback network between FB and COMP pins.
CURRENT REFERENCE
The IREF pin is used to set an internal current reference. This reference current sets IFB, IDELAY, ISS, and ILIMIT. A resistor to ground programs the current based on the 1.5 V output.
RIREF
IREF 1.5V
=
Typically, RIREF is set to 100 kΩ to program IREF = 15 μA.
Therefore,
IFB = IREF = 15 μA IDELAY = IREF = 15 μA ISS = IREF = 15 μA ILIMIT = 2/3 (IREF) = 10 μA
FAST ENHANCED PWM MODE
Fast enhanced PWM mode is intended to improve the transient response of the ADP3193A to a load step-up. In previous genera- tions of controllers, when a load step-up occurred, the controller could only respond to the load change after the PWM signal was turned on. Enhanced PWM mode allows the controller to immediately respond when a load step-up occurs. This allows the phases to respond more quickly when a load increase takes place.
DELAY TIMER
The delay times for the start-up timing sequence are set with a capacitor from the DELAY pin to ground. In UVLO or when EN is logic low, the DELAY pin is held at ground. After the UVLO and EN signals are asserted, the first delay time (TD1 in Figure 7) is initiated. A current flows out of the DELAY pin to charge CDLY. This current is equal to IREF, which is normally 15 μA. A comparator monitors the DELAY voltage with a threshold of 1.7 V. The delay time is therefore set by the IREF current charging a capacitor from 0 V to 1.7 V. This DELAY pin is used for multiple delay timings (TD1, TD3, and TD5) during the start-up sequence. In addition, DELAY is used for timing the current-limit latch-off, as explained in the Current-Limit, Short-Circuit, and Latch-Off Protection section.
SOFT START
The soft start times for the output voltage are set with a capacitor from the SS pin to ground. After TD1 and the phase detection cycle have been completed, the SS time (TD2 in Figure 7) starts.
The SS pin is disconnected from GND, and the capacitor is charged up to the 1.1 V boot voltage by the SS amplifier, which has an output current equal to IREF (normally 15 μA). The voltage at the FB pin follows the ramping voltage on the SS pin, limiting
the inrush current during startup. The soft start time depends on the value of the boot voltage and CSS.
When the SS voltage is within 100 mV of the boot voltage, the boot voltage delay time (TD3 in Figure 7) starts. The end of the boot voltage delay time signals the beginning of the second soft start time (TD4 in Figure 7). The SS voltage changes from the boot voltage to the programmed VID DAC voltage (either higher or lower) using the SS amplifier with the output current equal to IREF. The voltage of the FB pin follows the ramping voltage of the SS pin, limiting the inrush current during the transition from the boot voltage to the final DAC voltage. The second soft start time depends on the boot voltage, the programmed VID DAC voltage, and the CSS.
If EN is taken low or if VCC drops below UVLO, DELAY and SS are reset to ground to be ready for another soft start cycle.
Figure 8 shows typical start-up waveforms for the ADP3193A.
CH1 1V CH2 1V CH4 10V
CH3 1V M 1ms A CH1 700mV
1
2
3
4
T 40.4% 06652-
007
Figure 8. Typical Start-Up Waveforms (Channel 1: CSREF, Channel 2: DELAY, Channel 3: SS, Channel 4: Phase 1 Switch Node)
CURRENT-LIMIT, SHORT-CIRCUIT, AND LATCH-OFF PROTECTION
The ADP3193A compares a programmable current-limit setpoint to the voltage from the output of the current sense amplifier. The level of current limit is set with the resistor from the ILIMIT pin to ground. During operation, the current from ILIMIT is equal to 2/3 of IREF, resulting in 10 μA normally. This current through the external resistor sets the ILIMIT voltage, which is internally scaled to provide a current limit threshold of 82.6 mV/V. If the difference in voltage between CSREF and CSCOMP rises above the current-limit threshold, the internal current-limit amplifier controls the internal COMP voltage to maintain the average output current at the limit.
If the limit is reached and TD5 in Figure 7 has completed, a latch-off delay time starts, and the controller shuts down if the fault is not removed. The current-limit delay time shares the
DELAY pin timing capacitor with the start-up sequence timing.
However, during current limit, the DELAY pin current is reduced to IREF/4. A comparator monitors the DELAY voltage and shuts off the controller when the voltage reaches 1.7 V. Therefore, the current-limit latch-off delay time is set by the current of IREF/4 charging the delay capacitor from 0 V to 1.7 V. This delay is four times longer than the delay time during the start-up sequence.
The current-limit delay time starts only after the TD5 is complete. If there is a current limit during startup, the ADP3193A goes through TD1 to TD5, and then starts the latch-off time. Because the controller continues to cycle the phases during the latch-off delay time, the controller returns to normal operation and the DELAY capacitor is reset to GND if the short is removed before the 1.7 V threshold is reached.
The latch-off function can be reset by either removing and reapplying the supply voltage to the ADP3193A or by briefly toggling the EN pin low. To disable the short-circuit latch-off function, an external resistor should be placed in parallel with CDLY. This prevents the DELAY capacitor from charging up to the 1.7 V threshold. The addition of this resistor causes a slight increase in the delay times.
During startup, when the output voltage is below 200 mV, a secondary current limit is active. This is necessary because the voltage swing of CSCOMP cannot go below ground. This secondary current limit controls the internal COMP voltage to the PWM comparators to 1.5 V. This limits the voltage drop across the low-side MOSFETs through the current balance circuitry. An inherent per-phase current limit protects individual phases if one or more phases stop functioning because of a faulty component. This limit is based on the maximum normal mode COMP voltage. Typical overcurrent latch-off waveforms are shown in Figure 9.
CH1 1V CH2 1V CH4 10V
CH3 2V M 2ms A CH1 680mV
3 2 1
4
T 61.8% 06652-
008
Figure 9. Overcurrent Latch-Off Waveforms (Channel 1: CSREF, Channel 2: DELAY, Channel 3: COMP, Channel 4: Phase 1 Switch Node)
DYNAMIC VID
The ADP3193A can dynamically change the VID inputs while the controller is running. This allows the output voltage to change while the supply is running and supplying current to the load. This is commonly referred to as VID on-the-fly (OTF). A VID OTF can occur under light or heavy load conditions. The processor signals the controller by changing the VID inputs in multiple steps from the start code to the finish code. This change can be positive or negative.
When a VID input changes state, the ADP3193A detects the change and ignores the DAC inputs for a minimum of 400 ns.
This time prevents a false code due to logic skew while the eight VID inputs are changing. Additionally, the first VID change initiates the PWRGD and crowbar blanking functions for a minimum of 100 μs to prevent a false PWRGD or crowbar event. Each VID change resets the internal timer.
POWER-GOOD MONITORING
The power-good comparator monitors the output voltage via the CSREF pin. The PWRGD pin is an open-drain output whose high level, when connected to a pull-up resistor, indicates that the output voltage is within the specified nominal limits, which are based on the VID voltage setting. PWRGD goes low if the output voltage is outside of this specified range, if the VID DAC inputs are in no CPU mode, or if the EN pin is pulled low. PWRGD is blanked during a VID OTF event for a period of 200 μs to prevent false signals during the time the output is changing.
The PWRGD circuitry also incorporates an initial turn-on delay time (TD5) based on the DELAY timer. Prior to the SS voltage reaching the programmed VID DAC voltage and the PWRGD masking time finishing, the PWRGD pin is held low.
When the SS pin is within 100 mV of the programmed DAC voltage, the capacitor on the DELAY pin begins to charge.
A comparator monitors the DELAY voltage and enables PWRGD when the voltage reaches 1.7 V. The PWRGD delay time is, therefore, set by a current of IREF charging a capacitor from 0 V to 1.7 V.
OUTPUT CROWBAR
To protect the load and output components of the supply, the PWM outputs are driven low, which turns on the low-side MOSFETs when the output voltage exceeds the upper crowbar threshold. This crowbar action stops when the output voltage falls below the release threshold of approximately 300 mV.
Turning on the low-side MOSFETs pulls down the output as the reverse current builds up in the inductors. If the output overvoltage is due to a short in the high-side MOSFET, this action current limits the input supply or blows its fuse, protecting the microprocessor from being destroyed.
OUTPUT ENABLE AND UVLO
For the ADP3193A to begin switching, the input supply (VCC) to the controller must be higher than the UVLO threshold and the EN pin must be higher than its 0.85 V threshold. This initiates a system start-up sequence. If either UVLO or EN is less than its respective threshold, the ADP3193A is disabled.
This holds the PWM outputs at ground, shorts the DELAY capacitor to ground, and forces PWRGD and OD signals low.
In the application circuit (see Figure 10), the OD pin should be connected to the OD inputs of the ADP3120A drivers. Grounding OD disables the drivers such that both DRVH and DRVL are grounded. This feature is important in preventing the discharge of the output capacitors when the controller is shut off. If the driver outputs are not disabled, a negative voltage can be generated during output due to the high current discharge of the output capacitors through the inductors.
Table 4. VR11 and VR10.x VID Codes for the ADP3193A
VR11 DAC Codes: VIDSEL = High VR10.x DAC Codes: VIDSEL = Low
Output VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VID4 VID3 VID2 VID1 VID0 VID5 VID6
Off 0 0 0 0 0 0 0 0 N/A
Off 0 0 0 0 0 0 0 1 N/A
1.60000 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1
1.59375 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0
1.58750 0 0 0 0 0 1 0 0 0 1 0 1 1 0 1
1.58125 0 0 0 0 0 1 0 1 0 1 0 1 1 0 0
1.57500 0 0 0 0 0 1 1 0 0 1 0 1 1 1 1
1.56875 0 0 0 0 0 1 1 1 0 1 0 1 1 1 0
1.56250 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1
1.55625 0 0 0 0 1 0 0 1 0 1 1 0 0 0 0
1.55000 0 0 0 0 1 0 1 0 0 1 1 0 0 1 1
1.54375 0 0 0 0 1 0 1 1 0 1 1 0 0 1 0
1.53750 0 0 0 0 1 1 0 0 0 1 1 0 1 0 1
1.53125 0 0 0 0 1 1 0 1 0 1 1 0 1 0 0
1.52500 0 0 0 0 1 1 1 0 0 1 1 0 1 1 1
1.51875 0 0 0 0 1 1 1 1 0 1 1 0 1 1 0
1.51250 0 0 0 1 0 0 0 0 0 1 1 1 0 0 1
1.50625 0 0 0 1 0 0 0 1 0 1 1 1 0 0 0
1.50000 0 0 0 1 0 0 1 0 0 1 1 1 0 1 1
1.49375 0 0 0 1 0 0 1 1 0 1 1 1 0 1 0
1.48750 0 0 0 1 0 1 0 0 0 1 1 1 1 0 1
1.48125 0 0 0 1 0 1 0 1 0 1 1 1 1 0 0
1.47500 0 0 0 1 0 1 1 0 0 1 1 1 1 1 1
1.46875 0 0 0 1 0 1 1 1 0 1 1 1 1 1 0
1.46250 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1
1.45625 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0
1.45000 0 0 0 1 1 0 1 0 1 0 0 0 0 1 1
1.44375 0 0 0 1 1 0 1 1 1 0 0 0 0 1 0
1.43750 0 0 0 1 1 1 0 0 1 0 0 0 1 0 1
1.43125 0 0 0 1 1 1 0 1 1 0 0 0 1 0 0
1.42500 0 0 0 1 1 1 1 0 1 0 0 0 1 1 1
1.41875 0 0 0 1 1 1 1 1 1 0 0 0 1 1 0
1.41250 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1
1.40625 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0
1.40000 0 0 1 0 0 0 1 0 1 0 0 1 0 1 1
1.39375 0 0 1 0 0 0 1 1 1 0 0 1 0 1 0
1.38750 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1
1.38125 0 0 1 0 0 1 0 1 1 0 0 1 1 0 0
1.37500 0 0 1 0 0 1 1 0 1 0 0 1 1 1 1
1.36875 0 0 1 0 0 1 1 1 1 0 0 1 1 1 0
1.36250 0 0 1 0 1 0 0 0 1 0 1 0 0 0 1
1.35625 0 0 1 0 1 0 0 1 1 0 1 0 0 0 0
1.35000 0 0 1 0 1 0 1 0 1 0 1 0 0 1 1
1.34375 0 0 1 0 1 0 1 1 1 0 1 0 0 1 0
1.33750 0 0 1 0 1 1 0 0 1 0 1 0 1 0 1
1.33125 0 0 1 0 1 1 0 1 1 0 1 0 1 0 0
VR11 DAC Codes: VIDSEL = High VR10.x DAC Codes: VIDSEL = Low
Output VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VID4 VID3 VID2 VID1 VID0 VID5 VID6
1.32500 0 0 1 0 1 1 1 0 1 0 1 0 1 1 1
1.31875 0 0 1 0 1 1 1 1 1 0 1 0 1 1 0
1.31250 0 0 1 1 0 0 0 0 1 0 1 1 0 0 1
1.30625 0 0 1 1 0 0 0 1 1 0 1 1 0 0 0
1.30000 0 0 1 1 0 0 1 0 1 0 1 1 0 1 1
1.29375 0 0 1 1 0 0 1 1 1 0 1 1 0 1 0
1.28750 0 0 1 1 0 1 0 0 1 0 1 1 1 0 1
1.28125 0 0 1 1 0 1 0 1 1 0 1 1 1 0 0
1.27500 0 0 1 1 0 1 1 0 1 0 1 1 1 1 1
1.26875 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0
1.26250 0 0 1 1 1 0 0 0 1 1 0 0 0 0 1
1.25625 0 0 1 1 1 0 0 1 1 1 0 0 0 0 0
1.25000 0 0 1 1 1 0 1 0 1 1 0 0 0 1 1
1.24375 0 0 1 1 1 0 1 1 1 1 0 0 0 1 0
1.23750 0 0 1 1 1 1 0 0 1 1 0 0 1 0 1
1.23125 0 0 1 1 1 1 0 1 1 1 0 0 1 0 0
1.22500 0 0 1 1 1 1 1 0 1 1 0 0 1 1 1
1.21875 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0
1.21250 0 1 0 0 0 0 0 0 1 1 0 1 0 0 1
1.20625 0 1 0 0 0 0 0 1 1 1 0 1 0 0 0
1.20000 0 1 0 0 0 0 1 0 1 1 0 1 0 1 1
1.19375 0 1 0 0 0 0 1 1 1 1 0 1 0 1 0
1.18750 0 1 0 0 0 1 0 0 1 1 0 1 1 0 1
1.18125 0 1 0 0 0 1 0 1 1 1 0 1 1 0 0
1.17500 0 1 0 0 0 1 1 0 1 1 0 1 1 1 1
1.16875 0 1 0 0 0 1 1 1 1 1 0 1 1 1 0
1.16250 0 1 0 0 1 0 0 0 1 1 1 0 0 0 1
1.15625 0 1 0 0 1 0 0 1 1 1 1 0 0 0 0
1.15000 0 1 0 0 1 0 1 0 1 1 1 0 0 1 1
1.14375 0 1 0 0 1 0 1 1 1 1 1 0 0 1 0
1.13750 0 1 0 0 1 1 0 0 1 1 1 0 1 0 1
1.13125 0 1 0 0 1 1 0 1 1 1 1 0 1 0 0
1.12500 0 1 0 0 1 1 1 0 1 1 1 0 1 1 1
1.11875 0 1 0 0 1 1 1 1 1 1 1 0 1 1 0
1.11250 0 1 0 1 0 0 0 0 1 1 1 1 0 0 1
1.10625 0 1 0 1 0 0 0 1 1 1 1 1 0 0 0
1.10000 0 1 0 1 0 0 1 0 1 1 1 1 0 1 1
1.09375 0 1 0 1 0 0 1 1 1 1 1 1 0 1 0
Off N/A 1 1 1 1 1 0 1
Off N/A 1 1 1 1 1 0 0
Off N/A 1 1 1 1 1 1 1
Off N/A 1 1 1 1 1 1 0
1.08750 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1
1.08125 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0
1.07500 0 1 0 1 0 1 1 0 0 0 0 0 0 1 1
1.06875 0 1 0 1 0 1 1 1 0 0 0 0 0 1 0
1.06250 0 1 0 1 1 0 0 0 0 0 0 0 1 0 1
1.05625 0 1 0 1 1 0 0 1 0 0 0 0 1 0 0
1.05000 0 1 0 1 1 0 1 0 0 0 0 0 1 1 1
1.04375 0 1 0 1 1 0 1 1 0 0 0 0 1 1 0
1.03750 0 1 0 1 1 1 0 0 0 0 0 1 0 0 1
1.03125 0 1 0 1 1 1 0 1 0 0 0 1 0 0 0
1.02500 0 1 0 1 1 1 1 0 0 0 0 1 0 1 1
1.01875 0 1 0 1 1 1 1 1 0 0 0 1 0 1 0
1.01250 0 1 1 0 0 0 0 0 0 0 0 1 1 0 1
1.00625 0 1 1 0 0 0 0 1 0 0 0 1 1 0 0
1.00000 0 1 1 0 0 0 1 0 0 0 0 1 1 1 1
0.99375 0 1 1 0 0 0 1 1 0 0 0 1 1 1 0
VR11 DAC Codes: VIDSEL = High VR10.x DAC Codes: VIDSEL = Low
Output VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VID4 VID3 VID2 VID1 VID0 VID5 VID6
0.98750 0 1 1 0 0 1 0 0 0 0 1 0 0 0 1
0.98125 0 1 1 0 0 1 0 1 0 0 1 0 0 0 0
0.97500 0 1 1 0 0 1 1 0 0 0 1 0 0 1 1
0.96875 0 1 1 0 0 1 1 1 0 0 1 0 0 1 0
0.96250 0 1 1 0 1 0 0 0 0 0 1 0 1 0 1
0.95625 0 1 1 0 1 0 0 1 0 0 1 0 1 0 0
0.95000 0 1 1 0 1 0 1 0 0 0 1 0 1 1 1
0.94375 0 1 1 0 1 0 1 1 0 0 1 0 1 1 0
0.93750 0 1 1 0 1 1 0 0 0 0 1 1 0 0 1
0.93125 0 1 1 0 1 1 0 1 0 0 1 1 0 0 0
0.92500 0 1 1 0 1 1 1 0 0 0 1 1 0 1 1
0.91875 0 1 1 0 1 1 1 1 0 0 1 1 0 1 0
0.91250 0 1 1 1 0 0 0 0 0 0 1 1 1 0 1
0.90625 0 1 1 1 0 0 0 1 0 0 1 1 1 0 0
0.90000 0 1 1 1 0 0 1 0 0 0 1 1 1 1 1
0.89375 0 1 1 1 0 0 1 1 0 0 1 1 1 1 0
0.88750 0 1 1 1 0 1 0 0 0 1 0 0 0 0 1
0.88125 0 1 1 1 0 1 0 1 0 1 0 0 0 0 0
0.87500 0 1 1 1 0 1 1 0 0 1 0 0 0 1 1
0.86875 0 1 1 1 0 1 1 1 0 1 0 0 0 1 0
0.86250 0 1 1 1 1 0 0 0 0 1 0 0 1 0 1
0.85625 0 1 1 1 1 0 0 1 0 1 0 0 1 0 0
0.85000 0 1 1 1 1 0 1 0 0 1 0 0 1 1 1
0.84375 0 1 1 1 1 0 1 1 0 1 0 0 1 1 0
0.83750 0 1 1 1 1 1 0 0 0 1 0 1 0 0 1
0.83125 0 1 1 1 1 1 0 1 0 1 0 1 0 0 0
0.82500 0 1 1 1 1 1 1 0 N/A
0.81875 0 1 1 1 1 1 1 1 N/A
0.81250 1 0 0 0 0 0 0 0 N/A
0.80625 1 0 0 0 0 0 0 1 N/A
0.80000 1 0 0 0 0 0 1 0 N/A
0.79375 1 0 0 0 0 0 1 1 N/A
0.78750 1 0 0 0 0 1 0 0 N/A
0.78125 1 0 0 0 0 1 0 1 N/A
0.77500 1 0 0 0 0 1 1 0 N/A
0.76875 1 0 0 0 0 1 1 1 N/A
0.76250 1 0 0 0 1 0 0 0 N/A
0.75625 1 0 0 0 1 0 0 1 N/A
0.75000 1 0 0 0 1 0 1 0 N/A
0.74375 1 0 0 0 1 0 1 1 N/A
0.73750 1 0 0 0 1 1 0 0 N/A
0.73125 1 0 0 0 1 1 0 1 N/A
0.72500 1 0 0 0 1 1 1 0 N/A
0.71875 1 0 0 0 1 1 1 1 N/A
0.71250 1 0 0 1 0 0 0 0 N/A
0.70625 1 0 0 1 0 0 0 1 N/A
0.70000 1 0 0 1 0 0 1 0 N/A
0.69375 1 0 0 1 0 0 1 1 N/A
0.68750 1 0 0 1 0 1 0 0 N/A
0.68125 1 0 0 1 0 1 0 1 N/A
0.67500 1 0 0 1 0 1 1 0 N/A
0.66875 1 0 0 1 0 1 1 1 N/A
0.66250 1 0 0 1 1 0 0 0 N/A
0.65625 1 0 0 1 1 0 0 1 N/A
0.65000 1 0 0 1 1 0 1 0 N/A
0.64375 1 0 0 1 1 0 1 1 N/A
0.63750 1 0 0 1 1 1 0 0 N/A
0.63125 1 0 0 1 1 1 0 1 N/A
VR11 DAC Codes: VIDSEL = High VR10.x DAC Codes: VIDSEL = Low
Output VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VID4 VID3 VID2 VID1 VID0 VID5 VID6
0.62500 1 0 0 1 1 1 1 0 N/A
0.61875 1 0 0 1 1 1 1 1 N/A
0.61250 1 0 1 0 0 0 0 0 N/A
0.60625 1 0 1 0 0 0 0 1 N/A
0.60000 1 0 1 0 0 0 1 0 N/A
0.59375 1 0 1 0 0 0 1 1 N/A
0.58750 1 0 1 0 0 1 0 0 N/A
0.58125 1 0 1 0 0 1 0 1 N/A
0.57500 1 0 1 0 0 1 1 0 N/A
0.56875 1 0 1 0 0 1 1 1 N/A
0.56250 1 0 1 0 1 0 0 0 N/A
0.55625 1 0 1 0 1 0 0 1 N/A
0.55000 1 0 1 0 1 0 1 0 N/A
0.54375 1 0 1 0 1 0 1 1 N/A
0.53750 1 0 1 0 1 1 0 0 N/A
0.53125 1 0 1 0 1 1 0 1 N/A
0.52500 1 0 1 0 1 1 1 0 N/A
0.51875 1 0 1 0 1 1 1 1 N/A
0.51250 1 0 1 1 0 0 0 0 N/A
0.50625 1 0 1 1 0 0 0 1 N/A
0.50000 1 0 1 1 0 0 1 0 N/A
Off 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0
Off 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
