NCP5322A Two−Phase Buck Controller with Integrated Gate Drivers and 5−Bit DAC

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Two−Phase Buck Controller with Integrated Gate

Drivers and 5−Bit DAC

The NCP5322A is a second−generation, two−phase step down controller which incorporates all control functions required to power high performance processors and high current power supplies.

Proprietary multi−phase architecture guarantees balanced load current distribution and reduces overall solution cost in high current applications. Enhanced V²™ control architecture provides the fastest possible transient response, excellent overall regulation, and ease of use. The NCP5322A is a second−generation PWM controller because it optimizes transient response by combining traditional Enhanced V² with an internal PWM ramp and fast−feedback directly from V_CORE to the internal PWM comparator. These enhancements provide greater design flexibility, facilitate use and reduce output voltage jitter.

The NCP5322A multi−phase architecture reduces output voltage and input current ripple, allowing for a significant reduction in filter size and inductor values with a corresponding increase in inductor current slew rate. This approach allows a considerable reduction in input and output capacitor requirements, as well as reducing overall solution size and cost.

Features

•

^{Enhanced V}² Control Method with Internal Ramp

•

Internal PWM Ramp

•

Fast−Feedback Directly from V_CORE

•

5−Bit DAC with 1.0% Accuracy

•

Adjustable Output Voltage Positioning

•

4 On−Board Gate Drivers

•

200 kHz to 800 kHz Operation Set by Resistor

•

Current Sensed through Buck Inductors or Sense Resistors

•

Hiccup Mode Current Limit

•

Individual Current Limits for Each Phase

•

On−Board Current Sense Amplifiers

•

3.3 V, 1.0 mA Reference Output

•

5.0 V and/or 12 V Operation

•

On/Off Control (through Soft Start Pin)

•

Power Good Output with Internal Delay

•

Pb−Free Packages are Available

*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

Device Package Shipping†

ORDERING INFORMATION

NCP5322ADW SO−28L 26 Units/Rail

NCP5322ADWR2 SO−28L 1000 Tape & Reel SO−28L

DW SUFFIX CASE 751F

A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package

1

NCP5322A

AWLYYWWG

28

LGND V_ID0

V_CCH1 PWRGD

GATE(H)1 CS_REF

GND CS2

GATE(L)1 CS1

V_CCL1 V_DRP

V_CCL V_FB

R_OSC COMP

SS V_ID1

V_CCL2 V_ID2

GND2 V_ID4

GATE(L)2 V_ID3

GATE(H)2 I_LIM

V_CCH2 REF

PIN CONNECTIONS AND MARKING DIAGRAM

1 28

http://onsemi.com

NCP5322ADWG SO−28L

(Pb−Free)

26 Units/Rail

NCP5322ADWR2G SO−28L (Pb−Free)

1000 Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

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Figure 1. Application Diagram, 12 V Only to 1.6 V at 45 A, 220 kHz Recommended Components:

L1: Coiltronics P/N CTX15−14771 or T30−26 core with 3T of #16 AWG L2: Coiltronics P/N TBD or T50−52B with 5T of #16 AWG Bifilar C_INPUT: 3 × Sanyo Oscon 16SP270M (270 mF, 16 V, 4.4 A_RMS, 18 mW) C_OUT: 10 × Rubycon 16MBZ1500M10x20 (1500 mF, 16 V, 13 mW)

or 8 × Sanyo Oscon 4SP820M (820 mF, 4 V, 12 mW) C_CERAMICS: 12 × Panasonic ECJ−3YB0J106K (10 mF, 6.3 V) Q1−Q4: ON Semiconductor NTB85N03 (28 V, 85 A) L_VCC: Murata P/N BLM21P221SG (220 W at 100 MHz) SIG_GND

R_LIM2 1.0 k

R_LIM1

3.57 k C_REF 0.1 mF R_CSREF

49.9 k

SIG_GND C_CSREF 0.01 mF

CS_REF R_DRP1

21 k C_FBK2 470 pF

V_FB C_AMP 2.2 nF

C_CMP1 2.2 nF

SIG_GND

R_OSC 64.9 k C_VCC 1.0 mF +12 V

ENABLE

NCP5322A COMP V_FB V_DRP Cs1 CS2 CS_REF PWRGD V_ID0 V_ID1 V_ID2 V_ID3 V_ID4 I_LIM REF

R_OSC V_CCL V_CCL1 GL1 GND1 GH1 V_CCH1 LGND SS V_CCL2 GL2 GND2 GH2 V_CCH2

C_Q1 0.1 mF

Q1

Q2

C_Q3 0.1 mF

Q3

Q4 L1 300 nH

+ C_INPUT Electrolytics

L2 1.1 mH

+

C_OUT Electrolytics

C_CER Ceramics

L3 1.1 mH

SWNODE1 SWNODE2 CS1

CS2

R_CS1 75 k−142 k

R_CS2 75 k−142 k C_CS1

0.01 mF

C_CS2 0.01 mF R_FBK1

6.04 k

PWRGD V_ID0 V_ID1 V_ID2 V_ID3 V_ID4

SIG_GND D3

MBRA120LT3

C_SS 0.1 mF

SIG_GND C1

1.0 mF D1 BAT54SLT1

D2 BAT54SLT1

C2 1.0 mF

R3 330

D4 18 V

BZX84C18LT1

Q5 2N3904

SIG_GND C_VCCLx

1.0 mF

C_VCCHx 1.0 mF L_VCC

1.0 mF

SIG_GND

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Figure 2. Alternate Application Diagram, 5.0 V (with 12 V Bias) to 1.6 V at 45 A, 335 kHz Recommended Components:

L1: Coiltronics P/N CTX15−14771 or T30−26 core with 3T of #16 AWG L2: Coiltronics P/N CTX22−15401 or T50−52 with 5T of #16 AWG Bifilar L_VCC: Murata P/N BLM21P221SG (220 W at 100 MHz)

Q1−Q4: ON Semiconductor NTB85N03 (28 V, 85 A) SIG_GND

R_LIM2 1.0 k

R_LIM1

4.12 k C_REF 0.1 mF R_CSREF

33 k

SIG_GND C_CSREF 0.01 mF

CS_REF R_DRP1

10.7 k C_FBK2 470 pF

V_FB C_AMP 2.2 nF

C_CMP1 2.2 nF

SIG_GND

R_OSC 39.2 k C_VCC 1.0 mF +12 V

ENABLE

NCP5322A COMP V_FB V_DRP Cs1 CS2 CS_REF PWRGD V_ID0 V_ID1 V_ID2 V_ID3 V_ID4 I_LIM REF

R_OSC V_CCL V_CCL1 GL1 GND1 GH1 V_CCH1 LGND SS V_CCL2 GL2 GND2 GH2 V_CCH2

C_Q1 0.1 mF

Q1

Q2

C_Q3 0.1 mF

Q3

Q4 L1 300 nH

+ C_INPUT Electrolytics

L2 825 nH

+

C_OUT Electrolytics

C_CER Ceramics

L3 825 nH

SWNODE1 SWNODE2 CS1

CS2

R_CS1 50 k−100 k

R_CS2 50 k−100 k C_CS1

0.01 mF

C_CS2 0.01 mF R_FBK1

3.40 k

PWRGD V_ID0 V_ID1 V_ID2 V_ID3 V_ID4

SIG_GND D1

MBRA120LT3

C_SS 0.1 mF

SIG_GND SIG_GND

C_VCCLx 1.0 mF

C_VCCHx 1.0 mF +5.0 V

L_VCC

SIG_GND

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MAXIMUM RATINGS*

Rating Value Unit

Operating Junction Temperature 150 °C

Lead Temperature Soldering: Reflow: (SMD styles only) (Note 1): Pb Devices (Note 2): Pb−Free Devices

230 peak 260 Peak °C Package Thermal Resistance:

Junction−to−Case, R_q_JC Junction−to−Ambient, R_q_JA

15 75

°C/W

Storage Temperature Range −65 to +150 °C

ESD Susceptibility (Human Body Model) 2.0 kV

JEDEC Moisture Sensitivity Pb Devices

Pb−Free Devices

Level 1

Level 2 −

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

1. 60 second maximum above 183°C.

2. 60 second maximum above 217°C.

*The maximum package power dissipation must be observed.

MAXIMUM RATINGS

Pin Name V_MAX V_MIN I_SOURCE I_SINK

COMP 6.0 V −0.3 V 1.0 mA 1.0 mA

V_FB 6.0 V −0.3 V 1.0 mA 1.0 mA

V_DRP 6.0 V −0.3 V 1.0 mA 1.0 mA

CS1, CS2 6.0 V −0.3 V 1.0 mA 1.0 mA

CS_REF 6.0 V −0.3 V 1.0 mA 1.0 mA

R_OSC 6.0 V −0.3 V 1.0 mA 1.0 mA

PWRGD 6.0 V −0.3 V 1.0 mA 8.0 mA

VID Pins 6.0 V −0.3 V 1.0 mA 1.0 mA

I_LIM 6.0 V −0.3 V 1.0 mA 1.0 mA

REF 6.0 V −0.3 V 1.0 mA 20 mA

SS 6.0 V −0.3 V 1.0 mA 1.0 mA

V_CCL 16 V −0.3 V N/A 50 mA

V_CCHx 20 V −0.3 V N/A 1.5 A for 1.0 ms,

200 mA DC

V_CCLx 16 V −0.3 V N/A 1.5 A for 1.0 ms,

200 mA DC

GATE(H)x 20 V −2.0 V for 100 ns,

−0.3 V DC

1.5 A for 1.0 ms, 200 mA DC

GATE(L)x 16 V −2.0 V for 100 ns,

−0.3 V DC

1.5 A for 1.0 ms, 200 mA DC

GND1, GND2 0.3 V −0.3 V 2.0 A for 1.0 ms,

200 mA DC

N/A

LGND 0 V 0 V 50 mA N/A

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ELECTRICAL CHARACTERISTICS (0°C < T_A< 70°C; 0°C < T_J < 125°C; 9.0V < V_CCH1 = V_CCH2 < 20 V; 4.5 V <

V_CCL = V_CCL1 = V_CCL2 < 14V; C_GATE= 3.3nF, R_R(OSC) = 32.4kW, C_COMP = 1.0nF, C_REF = 0.1 mF, C_SS = 0.1 mF, DAC Code 10000 (1.45 V), C_VCC = 1.0mF; unless otherwise specified.)

Characteristic Test Conditions Min Typ Max Unit

Voltage Identification DAC

Accuracy (all codes) Measure V_FB = COMP ±1.0 %

V_ID4 V_ID3 V_ID2 V_ID1 V_ID0

1 1 1 1 1 − Fault Mode − Output Off V

1 1 1 1 0 − 1.089 1.100 1.111 V

1 1 1 0 1 − 1.114 1.125 1.136 V

1 1 1 0 0 − 1.139 1.150 1.162 V

1 1 0 1 1 − 1.163 1.175 1.187 V

1 1 0 1 0 − 1.188 1.200 1.212 V

1 1 0 0 1 − 1.213 1.225 1.237 V

1 1 0 0 0 − 1.238 1.250 1.263 V

1 0 1 1 1 − 1.262 1.275 1.288 V

1 0 1 1 0 − 1.287 1.300 1.313 V

1 0 1 0 1 − 1.312 1.325 1.338 V

1 0 1 0 0 − 1.337 1.350 1.364 V

1 0 0 1 1 − 1.361 1.375 1.389 V

1 0 0 1 0 − 1.386 1.400 1.414 V

1 0 0 0 1 − 1.411 1.425 1.439 V

1 0 0 0 0 − 1.436 1.450 1.465 V

0 1 1 1 1 − 1.460 1.475 1.490 V

0 1 1 1 0 − 1.485 1.500 1.515 V

0 1 1 0 1 − 1.510 1.525 1.540 V

0 1 1 0 0 − 1.535 1.550 1.566 V

0 1 0 1 1 − 1.559 1.575 1.591 V

0 1 0 1 0 − 1.584 1.600 1.616 V

0 1 0 0 1 − 1.609 1.625 1.641 V

0 1 0 0 0 − 1.634 1.650 1.667 V

0 0 1 1 1 − 1.658 1.675 1.692 V

0 0 1 1 0 − 1.683 1.700 1.717 V

0 0 1 0 1 − 1.708 1.725 1.742 V

0 0 1 0 0 − 1.733 1.750 1.768 V

0 0 0 1 1 − 1.757 1.775 1.793 V

0 0 0 1 0 − 1.782 1.800 1.818 V

0 0 0 0 1 − 1.807 1.825 1.843 V

0 0 0 0 0 − 1.832 1.850 1.869 V

Input Threshold V_ID4, V_ID3, V_ID2, V_ID1, V_ID0 1.00 1.25 1.50 V

Input Pull−up Resistance V_ID4, V_ID3, V_ID2, V_ID1, V_ID0 25 50 100 kW

Pull−up Voltage − 3.15 3.30 3.45 V

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ELECTRICAL CHARACTERISTICS (0°C < T_A< 70°C; 0°C < T_J < 125°C; 9.0V < V_CCH1 = V_CCH2 < 20 V; 4.5 V <

Power Good Output

Power Good Fault Delay CS_REF = DAC to DAC ±15% 60 120 240 ms

PWRGD Low Voltage CS_REF = 1.0 V, I_PWRGD = 4.0 mA − 0.25 0.40 V

Output Leakage Current CS_REF = 1.45 V, PWRGD = 5.5 V − 0.1 10 mA

Lower Threshold − −15 −12 −9.0 %

Upper Threshold − 9.0 12 15 %

Voltage Feedback Error Amplifier

V_FB Bias Current 1.0V < V_FB < 1.9V. Note 3. 9.0 10.3 11.5 mA

COMP Source Current COMP = 0.5V to 2.0V;

V_FB = 1.8V; DAC = 00000

15 30 60 mA

COMP Sink Current COMP = 0.5V to 2.0V;

V_FB = 1.9V; DAC = 00000

15 30 60 mA

COMP Clamp Voltage SS = 0.25 V to 2.5 V; V_FB = LGND;

Measure COMP

− − SS

Voltage V

COMP Max Voltage COMP Open; V_FB = 1.8V; DAC = 00000 2.4 2.7 − V

COMP Min Voltage COMP Open; V_FB = 1.9V; DAC = 00000 − 0.1 0.2 V

Transconductance −10mA < I_COMP < +10mA − 32 − mmho

Output Impedance − − 2.5 − MW

Open Loop DC Gain Note 4. 60 90 − dB

Unity Gain Bandwidth 0.01mF COMP Capacitor − 400 − kHz

PSRR @ 1.0kHz − − 70 − dB

Soft Start

Soft Start Charge Current 0.2 V ≤ SS ≤ 3.0 V 15 30 50 mA

Soft Start Discharge Current 0.2 V ≤ SS ≤ 3.0 V 4.0 7.5 13 mA

Hiccup Mode Charge/Discharge Ratio − 3.0 4.0 − −

Soft Start Clamp Voltage − 3.3 4.0 4.2 V

Soft Start Discharge Threshold Voltage − 0.20 0.27 0.34 V

PWM Comparators

Minimum Pulse Width CS1 = CS2 = CS_REF − 350 475 ns

Channel Start Up Offset V(CS1) = V(CS2) = V(V_FB) = V(CS_REF) = 0V;

Measure V(COMP) when GATE(H)1, GATE(H)2, switch high

0.3 0.4 0.5 V

GATE(H) and GATE(L)

High Voltage (AC) Measure V_CCLX − GATE(L)_X or V_CCHX − GATE(H)_X. Note 4.

− 0 1.0 V

Low Voltage (AC) Measure GATE(L)_{X or}GATE(H)_X. Note 4. − 0 0.5 V

Rise Time GATE(H)_X 1.0 V < GATE < 8.0 V; V_CCHX = 10 V − 35 80 ns

3. The V_FB Bias Current changes with the value of R_OSC per Figure 5.

4. Guaranteed by design. Not tested in production.

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ELECTRICAL CHARACTERISTICS (continued) (0°C < T_A< 70°C; 0°C < T_J < 125°C; 9.0V < V_CCH1 = V_CCH2 < 20 V; 4.5 V <

GATE(H) and GATE(L)

Rise Time GATE(L)_X 1.0 V < GATE < 8.0 V; V_CCLX = 10 V − 35 80 ns

Fall Time GATE(H)_X 8.0 V > GATE > 1.0 V; V_CCHX = 10 V − 35 80 ns

Fall Time GATE(L)_X 8.0 V > GATE > 1.0 V; V_CCLX = 10 V − 35 80 ns

GATE(H)x to GATE(L)x Delay GATE(H)_X < 2.0 V, GATE(L)_X > 2.0 V 30 65 110 ns GATE(L)x to GATE(H)x Delay GATE(L)_X < 2.0 V, GATE(H)_X > 2.0 V 30 65 110 ns GATE Pull−Down Force 100 mA into GATE with no power applied

to V_CCHX and V_CCLX = 2.0 V.

− 1.2 1.6 V

Oscillator

Switching Frequency Measure any phase (R_OSC = 32.4 k) 340 400 460 kHz

Switching Frequency Measure any phase (R_OSC = 63.4 k). Note 5. 150 200 250 kHz Switching Frequency Measure any phase (R_OSC = 16.2 k). Note 5. 600 800 1000 kHz

R_OSC Voltage − − 1.0 − V

Phase Delay − 165 180 195 deg

Adaptive Voltage Positioning V_DRP Output Voltage to DAC_OUT

Offset

CS1 = CS2 = CS_REF, V_FB = COMP Measure V_DRP − COMP

−15 − 15 mV

V_DRP Operating Voltage Range Measure V_DRP − GND, Note 5. − − 2.3 V

Maximum V_DRP Voltage (CS1 = CS2) − CS_REF = 50 mV, V_FB = COMP, Measure V_DRP − COMP

260 330 400 mV

Current Sense Amp to V_DRP Gain − 2.6 3.3 4.0 V/V

Current Sensing and Sharing

CS1−CS2 Input Bias Current V(CSx) = V(CS_REF) = 0 V − 0.1 2.0 mA

CS_REF Input Bias Current V(CSx) = V(CS_REF) = 0 V − 0.3 4.0 mA

Current Sense Amplifier Gain − 3.15 3.5 3.9 V/V

Current Sense Amp Mismatch (The Sum of Gain and Offset Errors.)

0 ≤ (CSx − CS_REF) ≤ 50 mV. Note 5. −5.0 − 5.0 mV

Current Sense Input to I_LIM Gain 0.25 V < I_LIM < 1.00 V 5.5 6.75 8.5 V/V

Current Limit Filter Slew Rate − 4.0 10 26 mV/ms

I_LIM Operating Voltage Range Note 5. − − 1.3 V

I_LIM Bias Current 0 < I_LIM < 1.0 V − 0.1 1.0 mA

Single Phase Pulse−by−Pulse Current Limit

Measure V(CSx) − V(CS_REF) that Trips Pulse−by−Pulse Limit

90 105 135 mV

Current Share Amplifier Bandwidth Note 5. 1.0 − − MHz

General Electrical Specifications

V_CCL Operating Current V_FB = COMP (no switching) − 22 26 mA

V_CCL1 or V_CCL2 Operating Current V_FB = COMP (no switching) − 4.5 5.5 mA

5. Guaranteed by design. Not tested in production.

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ELECTRICAL CHARACTERISTICS (continued) (0°C < T_A< 70°C; 0°C < T_J < 125°C; 9.0V < V_CCH1 = V_CCH2 < 20 V; 4.5 V <

General Electrical Specifications

V_CCH1 or V_CCH2 Operating Current V_FB = COMP (no switching) − 3.2 4.5 mA

V_CCL Start Threshold GATEs switching, Soft Start charging 4.05 4.3 4.5 V

V_CCL Stop Threshold GATEs stop switching, Soft Start discharging 3.75 4.1 4.35 V

V_CCL Hysteresis GATEs not switching, Soft Start not charging 100 200 300 mV

V_CCH1 Start Threshold GATEs switching, Soft Start charging 1.8 2.0 2.2 V

V_CCH1 Stop Threshold GATEs stop switching, Soft Start discharging 1.55 1.75 1.90 V

V_CCH1 Hysteresis GATEs not switching, Soft Start not charging 100 200 300 mV

Reference Output

V_REF Output Voltage 0mA < I(V_REF) < 1.0mA 3.2 3.3 3.4 V

Internal Ramp

Ramp Height @ 50% PWM Duty−Cycle

CS1 = CS2 = CS_REF. − 125 − mV

PACKAGE PIN DESCRIPTION

PACKAGE PIN #

PIN SYMBOL FUNCTION

SO−28L

1 COMP Output of the error amplifier and input for the PWM

comparators.

2 V_FB Voltage Feedback Pin. To use Adaptive Voltage Positioning

(AVP) select an offset voltage at light load and connect a resistor between V_FB and V_OUT. The input current of the V_FB pin and the resistor value determine output voltage offset for zero output current. Short V_FB to V_OUT for no AVP.

3 V_DRP Current sense output for AVP. The offset of this pin above the

DAC voltage is proportional to the output current. Connect a resistor from this pin to V_FB to set amount AVP or leave this pin open for no AVP. This pin’s maximum working voltage is 2.3 Vdc.

4−5 CS1−CS2 Current sense inputs. Connect current sense network for the

corresponding phase to each input. The input voltages to these pins must be kept within 105 mV of CS_REF or pulse−

by−pulse current limit will be tripped.

6 CS_REF Reference for Current Sense Amplifiers, input to the Power

Good comparators, and fast feedback connection to the PWM comparator. To balance input offset voltages between the inverting and noninverting inputs of the Current Sense Amplifiers, connect a resistor between CS_REF and the output voltage. The value should be 1/3 of the value of the resistors connected to the CSx pins. The input voltage to this pin must not exceed the maximum DAC (VID) setting by more than 100 mV or the internal PWM comparator may saturate.

7 PWRGD Power Good Output. Open collector output goes low when

CS_REF (V_OUT) is out of regulation.

8−12 V_ID4−V_ID0 Voltage ID DAC inputs. These pins are internally pulled up to 3.3V if left open.

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PACKAGE PIN DESCRIPTION (continued)

PACKAGE PIN #

FUNCTION PIN SYMBOL

SO−28L PIN SYMBOL FUNCTION

13 I_LIM Sets threshold for current limit. Connect to reference through

a resistive divider. This pin’s maximum working voltage is 1.3 Vdc.

14 REF Reference output. Decouple with 0.1mF to LGND.

15 V_CCH2 Power for GATE(H)2.

16 GATE(H)2 High side driver #2.

17 GND2 Return for #2 drivers.

18 GATE(L)2 Low side driver #2.

19 V_CCL2 Power for GATE(L)2.

20 SS Soft Start capacitor pin. The Soft Start capacitor controls

both Soft Start time and hiccup mode frequency. The COMP pin is clamped below Soft Start during Start−Up and hiccup mode.

21 LGND Return for internal control circuits and IC substrate connection.

22 V_CCH1 Power for GATE(H)1. UVLO Sense for High Side Driver sup-

ply connects to this pin.

23 GATE(H)1 High side driver #1.

24 GND1 Return #1 drivers.

25 GATE(L)1 Low side driver #1.

26 V_CCL1 Power for GATE(L)1.

27 V_CCL Power for internal control circuits. UVLO Sense for Logic

connects to this pin.

28 R_OSC A resistor from this pin to ground sets operating frequency

and V_FB bias current.

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Figure 3. Block Diagram

+ −

VID0 VID1 VID2 VID3 VID4

5−Bit DAC

OUT 11111

3.3 V REF

VCCL3.3 VVFB Current GenROSC OSC LGND CSREF

PH1 PH2

− +

Error Amp − +

COMP Shutdown VFB_BIAS − +

CS1 CS2

GCSA1 3.50 GCSA2 3.50

CO1 CO2Σ Summer

GVDRP 0.94 GILIM 1.93

Σ Summer + − − +

Slew Rate Limit ILIM

Current Limit Shutdown VCCL FaultVCCL

+ − Start Stop4.3 V 4.1 V− + VCCH1 FaultVCCH1

+ − Start Stop2.0 V 1.75 V

SU Offset 0.4 V

+

SU Offset + −

RAMP1 CO1 − +

+

SU Offset + −

RAMP2 CO2

PWMC1

S R

RESET Dominant Q Q

D F/F

Non−Overlap Gate Driver

PH1

VCCH1 GATE(H)1 VCCL1 GATE(L)1 GND1 S R

RESET Dominant Q Q

D F/F

Non−Overlap Gate Driver

PH2

VCCH2 GATE(H)2 VCCL2 GATE(L)2 GND2

MAXC1 PWMC2 MAXC2

0.367 V − + − +

CSREF DAC OUT

+12% −12%

Delay 120 ms

PWRGD VDRP +−COMP Clamp S R

Q Q

D F/F + −

+ −

SS Discharge Threshold 0.27 V

SET Dominant RESET

Fault SS Discharge Current 7.5 mA

ON ON

SS Charge Current 30 mA VCCLSoft Start SS Clamp 4.0 V

− + + −

+ − − +

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 4. Oscillator Frequency vs. R_OSC Value Figure 5. V_FB Bias Current vs. R_OSC Value

Figure 6. GATE(H) Rise Time vs. Load Capacitance Measured from 1.0 V to 4.0 V with V_CC at 5.0 V

Figure 7. GATE(H) Fall Time vs. Load Capacitance Measured from 4.0 V to 1.0 V with V_CC at 5.0 V

Figure 8. GATE(L) Rise Time vs. Load Capacitance Measured from 1.0 V to 4.0 V with V_CC at 5.0 V

Figure 9. GATE(L) Fall Time vs. Load Capacitance Measured from 4.0 V to 1.0 V with V_CC at 5.0 V

Frequency (kHz)

100

R_OSC Value (kW) 300

400 500 600 700 800 900

200

10 20 30 40 50 60 70

0

Time, ns

0

Load Capacitance, nF 20

60 80 100 120

2 4 6 8 10 12 14 16

40

0

Time, ns

0

60 80 100 120

2 4 6 8 10 12 14 16

40 0

Time, ns

0

60 80 100 120

2 4 6 8 10 12 14 16

40

0

Time, ns

0

60 80 100 120

2 4 6 8 10 12 14 16

40 10 VFB Bias Current, mA

0

R_OSC Value, kW 5

10 15 20 25

20 30 40 50 60 70 80

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APPLICATIONS INFORMATION

Overview

The NCP5322A DC/DC controller from ON Semiconductor was developed using the Enhanced V² topology to meet requirements of low voltage, high current loads with fast transient requirements. Enhanced V² combines the original V² topology with peak current−mode control for fast transient response and current sensing capability. The addition of an internal PWM ramp and implementation of fast−feedback directly from V_CORE has improved transient response and simplified design. The NCP5322A includes Power Good (PWRGD) and MOSFET gate drivers to provide a “fully integrated solution” to simplify design, minimize circuit board area, and reduce overall system cost.

Two advantages of a multi−phase converter over a single−phase converter are current sharing and increased apparent output frequency. Current sharing allows the designer to use less inductance in each phase than would be required in a single−phase converter. The smaller inductor will produce larger ripple currents but the total per phase power dissipation is reduced because the RMS current is lower.

Transient response is improved because the control loop will measure and adjust the current faster in a smaller output inductor. Increased apparent output frequency is desirable because the off time and the ripple voltage of the two−phase converter will be less than that of a single−phase converter.

Fixed Frequency Multi−Phase Control

In a multi−phase converter, multiple converters are connected in parallel and are switched on at different times.

This reduces output current from the individual converters and increases the apparent ripple frequency. Because several converters are connected in parallel, output current can ramp up or down faster than a single converter (with the same value output inductor) and heat is spread among multiple components.

The NCP5322A controller uses two−phase, fixed frequency, Enhanced V² architecture to measure and control

currents in individual phases. Each phase is delayed 180° from the previous phase. Normally, GATE(H) transitions to a high voltage at the beginning of each oscillator cycle.

Inductor current ramps up until the combination of the current sense signal, the internal ramp and the output voltage ripple trip the PWM comparator and bring GATE(H) low.

Once GATE(H) goes low, it will remain low until the beginning of the next oscillator cycle. While GATE(H) is high, the Enhanced V² loop will respond to line and load variations. On the other hand, once GATE(H) is low, the loop can not respond until the beginning of the next PWM cycle.

Therefore, constant frequency Enhanced V² will typically respond to disturbances within the off−time of the converter.

The Enhanced V² architecture measures and adjusts the output current in each phase. An additional input (CSn) for inductor current information has been added to the V² loop for each phase as shown in Figure 10. The triangular inductor current is measured differentially across RS, amplified by CSA and summed with the Channel Startup Offset, the Internal Ramp, and the Output Voltage at the non−inverting input of the PWM comparator. The purpose of the Internal Ramp is to compensate for propagation delays in the NCP5322A. This provides greater design flexibility by allowing smaller external ramps, lower minimum pulse widths, higher frequency operation, and PWM duty cycles above 50% without external slope compensation. As the sum of the inductor current and the internal ramp increase, the voltage on the positive pin of the PWM comparator rises and terminates the PWM cycle. If the inductor starts a cycle with higher current, the PWM cycle will terminate earlier providing negative feedback. The NCP5322A provides a CSn input for each phase, but the CS_REF and COMP inputs are common to all phases. Current sharing is accomplished by referencing all phases to the same CS_REF and COMP pins, so that a phase with a larger current signal will turn off earlier than a phase with a smaller current signal.

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Figure 10. Enhanced V² Control Employing Resistive Current Sensing and Additional Internal Ramp

SWNODE Ln RLn +

RSn

CSn

CSA COn

CS_REF

+ V_OUT (V_CORE)

“Fast−Feedback”

Connection +

PWM COMP

To F/F Reset Channel

Start−Up Offset

+ DAC E.A.

Out V_FB

COMP

Internal Ramp

+

n = 1 or 2

− +

Enhanced V² responds to disturbances in VCORE by employing both “slow” and “fast” voltage regulation. The internal error amplifier performs the slow regulation.

Depending on the gain and frequency compensation set by the amplifier’s external components, the error amplifier will typically begin to ramp its output to react to changes in the output voltage in 1−2 PWM cycles. Fast voltage feedback is implemented by a direct connection from V_CORE to the non−inverting pin of the PWM comparator via the summation with the inductor current, internal ramp, and Offset. A rapid increase in load current will produce a negative offset at V_CORE and at the output of the summer.

This will cause the PWM duty cycle to increase almost instantly. Fast feedback will typically adjust the PWM duty cycle in 1 PWM cycle.

As shown in Figure 10, an internal ramp (nominally 125 mV at a 50% duty cycle) is added to the inductor current ramp at the positive terminal of the PWM comparator. This additional ramp compensates for propagation time delays from the current sense amplifier (CSA), the PWM comparator, and the MOSFET gate drivers. As a result, the minimum ON time of the controller is reduced and lower duty cycles may be achieved at higher frequencies. Also, the additional ramp reduces the reliance on the inductor current ramp and allows greater flexibility when choosing the output inductor and the R_CSnC_CSn (n = 1 or 2) time constant of the feedback components from V_CORE to the CSn pin.

Including both current and voltage information in the feedback signal allows the open loop output impedance of the power stage to be controlled. When the average output current is zero, the COMP pin will be:

VCOMP+VOUT @ 0 A)Channel_Startup_Offset )Int_Ramp)GCSA@Ext_Rampń2 Int_Ramp is the “partial” internal ramp value at the corresponding duty cycle, Ext_Ramp is the peak−to−peak

external steady−state ramp at 0 A, GCSA is the Current Sense Amplifier Gain (nominally 3.5 V/V), and the Channel Startup Offset is typically 0.40 V. The magnitude of the Ext_Ramp can be calculated from:

Ext_Ramp+D@(VIN*VOUT)ń(RCSn@CCSn@fSW) For example, if V_OUT at 0 A is set to 1.630 V with AVP and the input voltage is 12.0 V, the duty cycle (D) will be 1.630/12.0 or 13.6%. Int_Ramp will be 125 mV •13.6/50 = 34 mV. Realistic values for R_CSn, C_CSn and f_SW are 60 kW, 0.01 mF, and 220 kHz − using these and the previously mentioned formula, Ext_Ramp will be 10.6 mV.

VCOMP+1.630 V)0.40 V)34 mV )3.5 VńV@10.6 mVń2 +2.083 Vdc.

If the COMP pin is held steady and the inductor current changes, there must also be a change in the output voltage.

Or, in a closed loop configuration when the output current changes, the COMP pin must move to keep the same output voltage. The required change in the output voltage or COMP pin depends on the scaling of the current feedback signal and is calculated as:

DV+RS@GCSA@DIOUT.

The single−phase power stage output impedance is:

Single Stage Impedance+DVOUTńDIOUT+RS@GCSA The multi−phase power stage output impedance is the single−phase output impedance divided by the number of phases. The output impedance of the power stage determines how the converter will respond during the first few microseconds of a transient before the feedback loop has repositioned the COMP pin.

The peak output current can be calculated from: